tmp19a44fda TOSHIBA Semiconductor CORPORATION, tmp19a44fda Datasheet - Page 374

• Manufacturer Part Number: tmp19a44fda
• Description: 32bit Tx System Risc
• Manufacturer: TOSHIBA Semiconductor CORPORATION

Serial Channel (SIO)
SC0CR
14.3.2.3
<RB8>:
<EVEN>:
<PE>:
<OERR>:
<PERR>:
<FERR>:
<SCLKS>:
<IOC>:
(Note)
bit Symbol
Read/Writ
e
After reset
Function
Every error flag is cleared when read.
Control Register
Specifies parity condition.
“0”: Odd parity
“1”: Even parity
Parity is available for 7 bit/ 8 bit UART mode.
Enables or disables parity.
Parity is available for 7 bit/ 8 bit UART mode.
Indicates error flags (overrun error flag, parity error/ underrun error flag and framing error flag).
(Note)
I/O interface input clock selection.
“0”: Baud rate generator
“1”: SCLK0 pin input
Indicates 9
“0”: Data send/receive at rising edges of SCLK0
“1”: Data send/receive at falling edges of SCLK0
Clock edge selection for data transmission/ reception
Bit 8
(for
UART)
Receive
data
RB8
R
0
7
th
received bit in 9 bit UART mode.
Parity
(for
UART)
0: Odd
1: Even
EVEN
6
0
TMP19A44(rev1.3) 14-22
R/W
Add
parity
(for
UART)
1: Enable
0: Disable
PE
5
0
0: Normal operation
Overrun
R (cleared to "0" when read)
OERR
4
0
Parity/
under-
run
1: Error
PERR
3
0
Framing
FERR
2
0
TMP19A44
SCLKS
SCLK0
SCLK0
0:
1:
1
0
R/W
(for I/O
1: SCLK0
0: Baud
interfac
e)
input
rate
generator
2010-04-01
IOC
pin
0
0