tmp19a44fda TOSHIBA Semiconductor CORPORATION, tmp19a44fda Datasheet - Page 583

• Manufacturer Part Number: tmp19a44fda
• Description: 32bit Tx System Risc
• Manufacturer: TOSHIBA Semiconductor CORPORATION

「EXTEST Instruction ：CPU is working and note the terminal input, please when using it.」
「EXTEST Instruction：Please test after releasing system reset when using it.」
JTAG Interface
23.4 Instructions Supported by the JTAG Controller Cells
This section describes the instructions supported by the JTAG controller cells of the TMP19A44.
23.4.1
The EXTEST instruction is used for external interconnect test. If this instruction is issued, the BSR cells
at output pins output test patterns in the Update-DR state, and the BSR cells at input pins capture test
results in the Capture-DR state.
Before the EXTEST instruction is selected, the boundary scan register is usually initialized using the
SAMPLE/PRELOAD instruction. If the boundary scan register has not been initialized, there is the
possibility that indeterminate data will be transmitted in the Update-DR state and bus conflicts may
occur between ICs. Fig. 23-8 shows the flow of data while the EXTEST instruction is selected.
The basic external interconnect test procedure is as follows:
1.
2.
3.
4.
5.
6.
7.
8.
Repeat steps 6 through 8 for each test pattern.
Input
TDI
Initialize the TAP controller to put it in the Test-Logic-Reset state.
Load the SAMPLE/PRELOAD instruction into the instruction register. This allows the boundary
scan register to be connected between TDI and TDO.
Initialize the boundary scan register by shifting in determinate data.
Load the initial test data into the boundary scan register.
Load the EXTEST instruction into the instruction register.
Capture the data applied to the input pin and input it into the boundary scan register.
Shift out the captured data while simultaneously shifting in the next test pattern.
Output to the output pin the test pattern that was shifted into the boundary scan register for output.
EXTEST Instruction
Fig. 23-8 Flow of Data While the EXTEST Instruction Is Selected
TMP19A44(rev1.3) 23-11
Boundary scan path
Internal logic
TMP19A44
Output
TDO
2010-04-01