tmp19a44fda TOSHIBA Semiconductor CORPORATION, tmp19a44fda Datasheet - Page 663

• Manufacturer Part Number: tmp19a44fda
• Description: 32bit Tx System Risc
• Manufacturer: TOSHIBA Semiconductor CORPORATION

Electrical Characteristics
SCK Output Mode/
SCL Input Mode
Active-Low SCK
OUTPUT DATA
27.8 Serial Channel Timing
(1) I/O Interface mode（DVCC3=2.7V to 3.6V）
* SCLK rise or fall: Measured relative to the programmed active edge of SCLK.
Active-High
SCLK period
SCLK Clock High width(input)
SCLK Clock Low width (input)
TxD data to SCLK rise or fall*
TxD data hold after SCLK rise or fall*
RxD data valid to SCLK rise or fall*
RxD data hold after SCLK rise or fall*
SCLK period
TxD data to SCLK rise or fall*
TxD data hold after SCLK rise or fall*
RxD data valid to SCLK rise or fall*
RxD data hold after SCLK rise or fall*
Input Mode
INPUT DATA
SCLK
SCLK
RxD
TxD
In the table below, the letter x represents the fsys cycle period, which varies depending on the
programming of the clock gear function.
1) SCLK input mode（SIO0 to SIO2）
2) SCLK output mode （SIO0 to SIO2）
Parameter
Parameter
t
t
OSS
SRD
VALID
0
t
0
SCY
tSCY
TscH
TscL
tOSS
tOHS
tSRD
tHSR
tSCY
tOSS
tOHS
tSRD
tHSR
TMP19A44 (rev1.3) 27-23
Sym
Sym
bol
bol
t
SCY
t
t
SCY
SCY
/2 – 2x - 45
t
x + 30
t
t
SCY
SCY
SCY
Min
VALID
Min
30
45
6x
4x
/2 - 20
/2 - 20
1
Equation
Equation
0
1
/2
/2
/2
t
HSR
t
OHS
Max
Max
150
40/ 80 MHz
40/ 80 MHz
Min
-20
100
75
75
75
30
55
Min
VALID
45
45
45
0
2
2
Max
Max
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
TMP19A44
Unit
Unit
VALID
3
3
2010-04-01