tmp19a44fda TOSHIBA Semiconductor CORPORATION, tmp19a44fda Datasheet - Page 436

• Manufacturer Part Number: tmp19a44fda
• Description: 32bit Tx System Risc
• Manufacturer: TOSHIBA Semiconductor CORPORATION

Serial Bus Interface (SBI)
16.5.4
16.5.5
When the SBI is configured to operate as a slave device, the slave address <SA6:0> and <ALS> must
be set at I2CAR. Setting <ALS> to "0" selects the address recognition mode.
Setting SBICR2<MST> to "1" configures the SBI to operate as a master device.
Setting <MST> to "0" configures the SBI as a slave device. <MST> is cleared to "0" by the hardware
when the stop condition has been detected on the bus or when arbitration has been lost.
Internal SCL output (Master A)
Internal SCL output (Master B)
SCL line
Clock Synchronization
The I
that pulls its clock line to the "L" level overrides other masters producing the "H" level on their
clock lines. This must be detected and responded by the masters producing the "H" level.
Clock synchronization assures correct data transfer on a bus that has two or more masters.
For example, the clock synchronization procedure for a bus with two masters is shown below.
At point a, Master A pulls its internal SCL output to the "L" level, bringing the SCL bus line to the
"L" level. Master B detects this transition, resets its "H" level period counter, and pulls its internal
SCL output level to the "L" level.
Master A completes counting of its "L" level period at point b, and brings its internal SCL output to
the "H" level. However, Master B still keeps the SCL bus line at the "L" level, and Master A stops
counting of its "H" level period counting. After Master A detects that Master B brings its internal
SCL output to the "H" level and brings the SCL bus line to the "H" level at point c, it starts
counting of its "H" level period.
This way, the clock on the bus is determined by the master with the shortest "H" level period and
the master with the longest "L" level period among those connected to the bus.
Slave Addressing and Address Recognition Mode
Configuring the SBI as a Master or a Slave
2
C bus is driven by using the wired-AND connection due to its pin structure. The first master
Fig. 16.4 Example of Clock Synchronization
TMP19A44 (rev1.3) 16-12
a
Reset high-level
period counting
Wait for high-level
period counting
b
c
Start high-level period counting
TMP19A44
2010-04-01