tmp19a44fda TOSHIBA Semiconductor CORPORATION, tmp19a44fda Datasheet - Page 616

• Manufacturer Part Number: tmp19a44fda
• Description: 32bit Tx System Risc
• Manufacturer: TOSHIBA Semiconductor CORPORATION

Flash Memory Operation
(Note 1) Command sequences are executed from outside the flash memory area.
(Note 2) The interval between bus write cycles for this device must be 15 system clock cycles or
(Note 3) Between the bus write cycles, never use any load command (such as LW, LH, or LB) to the
(Note 4) The SYNC command must be executed immediately after the SW command for each bus
(Note 5) For the command sequencer to recognize a command, the device must be in the read mode
(Note 6) Upon issuing a command, if any address or data is incorrectly written, be sure to perform a
3)
4) Automatic Page Programming
Reset
Hardware reset
The flash memory has a reset input as the memory block and it is connected to the CPU reset
signal. Therefore, when the RESET input pin of this device is set to V
due to any overflow of the watch dog timer, the flash memory will return to the read mode
terminating any automatic operation that may be in progress. The CPU reset is also used in
returning to the read mode when an automatic operation is abnormally terminated or when any
mode set by a command is to be canceled. It should also be noted that applying a hardware reset
during an automatic operation can result in incorrect rewriting of data. In such a case, be sure to
perform the rewriting again.
Refer to Section 24.2.1 "Reset Operation" for CPU reset operations. After a given reset input, the
CPU will read the reset vector data from the flash memory and starts operation after the reset is
removed.
Writing to a flash memory device is to make "1" data cells to "0" data cells. Any "0" data cell
cannot be changed to a "1" data cell. For making "0" data cells to "1" data cells, it is necessary to
perform an erase operation.
The automatic page programming function of this device writes data in 128 word blocks. A 128
word block is defined by a same [31:9] address and it starts from the address [8:0] = 0 and ends at
the address [8:0] = 0x1FF. This programming unit is hereafter referred to as a "page."
longer. The command sequencer in the flash memory device requires a certain time period to
recognize a bus write cycle. If more than one bus write cycles are executed within this time
period, normal operation cannot be expected. For adjusting the applicable bus write cycle
interval using a software timer to be operated at the operating frequency, use the section 10)
"ID-Read" to check for the appropriateness.
flash memory or perform a DMA transmission by specifying the flash area as the source
address. Also, don't execute a Jump command to the flash memory. While a command
sequence is being executed, don't generate any interrupt such as maskable interrupts (except
debug exceptions when a DSU probe is connected).
If such an operation is made, it can result in an unexpected read access to the flash memory
and the command sequencer may not be able to correctly recognize the command. While it
could cause an abnormal termination of the command sequence, it is also possible that the
written command is incorrectly recognized.
write cycle.
prior to executing the command. Be sure to check before the first bus write cycle that the
FLCS[0]R <FlashBusy> bit is set to "1." It is recommended to subsequently execute a Read
command.
system reset operation or issue a reset command to return to the read mode again.
TMP19A44 (rev1.3)24-31
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TMP19A44
or when the CPU is reset
2010-04-01