tmp19a44fda TOSHIBA Semiconductor CORPORATION, tmp19a44fda Datasheet - Page 99

• Manufacturer Part Number: tmp19a44fda
• Description: 32bit Tx System Risc
• Manufacturer: TOSHIBA Semiconductor CORPORATION

Exceptions/Interrupts
(Note 1) When this bit is set:
(Note 2) When this bit is set:
(Note 3) The IE bit is not automatically set or cleared by the interrupt response sequence or the
(Note 4) An interrupt vector address differs depending on combination of the BEV bit in the Status
(Note 5) Writing 0 clears this bit. Writing 1 to this bit is ignored.
(Note 6) Write “1” when using CP0 in user mode. In Kernel mode, CP0 is always available, regardless
ERET instruction. (This bit is cleared upon reset.)
register and the IV bit in the Cause register.
of the value of the CU0 bit.
・
・  I nterrupts are disabled.
・
・  T he processor is running in Kernel mode.
・  I nterrupts are disabled.
・  T he EPC register and the BD bit in the Cause register will not be updated if another
exception is taken.
The processor is running is Kernel mode.
The ERET instruction will use the return address held in the ErrorEPC register.
IV = 0
IV = 1
TMP19A44(rev1.3) 6-49
0x8000_0180
0x8000_0200
BEV = 0
0xBFC0_0380
0xBFC0_0400
BEV = 1
TMP19A44
2010-04-01