tmp19a44fda TOSHIBA Semiconductor CORPORATION, tmp19a44fda Datasheet - Page 59

• Manufacturer Part Number: tmp19a44fda
• Description: 32bit Tx System Risc
• Manufacturer: TOSHIBA Semiconductor CORPORATION

Exceptions/Interrupts
6.1.3.4
6.1.3.5
Status<BEV> bit and Cause<IV> bit.
order to prevent the same interrupt from occurring.
change the bit from “1”.
addresses of interrupt exceptions and other exceptions can be distinguished.
exception/ interrupt generated. You need to program the exception handler.
The CPU branches off to the exception vector address (exception handler) in detecting an exception/ interrupt.
The exception vector addresses differ depending on the exceptions/ interrupts or the settings in the CP0 register
The Status<BEV> bit is set to “1” after reset. If you set the exception vector address to the internal ROM, do not
The Cause<IV> bit is undefined after reset. Setting this bit to “1” is required. By setting this bit to “1” the vector
The following table lists the vector addresses.
The exception handler executes exception/ interrupt processing. The processing varies depending on the
When using the exception handler for interrupts, processing (i.e. clearing interrupt request) may be required in
See “6.5 hardware interrupt” for details.
Branch to Exception handler
Execution of Exception Handler Program
RESET,NMI
Debug exception
Interrupt (Cause<IV>=0)
Interrupt (Cause<IV>=1)
Other exceptions
Exceptions/ interrupts
Table 6.4 Exception vector address (virtual)
TMP19A44(rev1.3) 6-9
Status<BEV>=0
0xBFC0_0000
0xBFC0_0480
0x8000_0180
0x8000_0200
0x8000_0180
Status<BEV>=1
0xBFC0_0000
0xBFC0_0480
0xBFC0_0380
0xBFC0_0380
0xBFC0_0400
TMP19A44
2010-04-01