tmp19a44fda TOSHIBA Semiconductor CORPORATION, tmp19a44fda Datasheet - Page 332

• Manufacturer Part Number: tmp19a44fda
• Description: 32bit Tx System Risc
• Manufacturer: TOSHIBA Semiconductor CORPORATION

32-bit Input Capture (TMRC)
12.2.5
12.2.6
This is a 32-bit register for capturing count values of the time base timer by using capture factors as
triggers. If a capture operation is performed, the capture interrupt INTCAPn is generated. Four interrupt
requests INTCAP0 through INTCAP3 are then notified to the interrupt controller.
This is a 32-bit register for specifying a compare value. TMRC has eight built-in compare registers,
TCCMP0 through TCCMP7. If values set in these compare registers match the value of the time base
timer TBT, the match detection signal of a comparator becomes active. "Compare enable" or "compare
disable" can be specified with the compare control register CMPCTL<CMPENn>.
Each compare register has a double-buffer structure, that is, TCCMPn forms a pair with a register buffer
"n." "Enable" or "disable" of the double buffers is controlled by the compare control register CMPCTL
<CMPRDEn>. If <CMPRDEn> is set to "0," the double buffers are disabled. If <CMPRDEn> is set to
"1," they are enabled.
If the double buffers are enabled, data transfer from the register buffer "n" to the compare register
TCCMPn takes place when the value of TBT matches that of TCCMPn.
Because TCCMPn is indeterminate when a reset is performed, it is necessary to prepare and write data
in advance. A reset initializes CMPCTL <CMPRDEn> to "0" and disables the double buffers. To use the
double buffers, data must be written to the compare register, <CMPRDEn> must be set to "1," and then
the following data must be written to the register buffer.
TCCMPn and the register buffer are assigned to the same address. If <CMPRDEn> is "0," the same
value is written to TCCMPn and each register buffer. If <CMPRDEn> is "1," data is written to each
register buffer only. Therefore, to write an initial value to the compare register, it is necessary to set the
double buffers to "disable."
32-bit Capture Register
32-bit Compare Register
TMP19A44 (rev1.3) 12-7
TMP19A44
2010-04-01