tmp19a44fda TOSHIBA Semiconductor CORPORATION, tmp19a44fda Datasheet - Page 266

• Manufacturer Part Number: tmp19a44fda
• Description: 32bit Tx System Risc
• Manufacturer: TOSHIBA Semiconductor CORPORATION

(Note)
DMA Controller (DMAC)
10.2.2
10.2.3
If the snoop function is not used, the TX19A/ H1 processor core does not open the data bus
to the DMAC. If the data bus is closed and the internal RAM or ROM is designated as a
DMAC source or destination, an acknowledgment signal will not be returned in response to
a DMAC transfer bus cycle and, as a result, the bus will lock.
Fig. 10.2 shows the internal blocks of the DMAC.
The TX19A/ H1 processor core has a snoop function. If the snoop function is activated, the TX19A/ H1
processor core opens the core's data bus to the DMAC and suspends its own operation until the DMAC
withdraws a request for bus control authority. If the snoop function is enabled, the DMAC can access
the internal RAM and ROM and therefore designate the RAM or ROM as a source or destination.
If the snoop function is not used, the DMAC cannot access the internal RAM or ROM. However, the G-
Bus is opened to the DMAC. If the TX19A/ H1 processor core attempts to access memory space 1by
way of the G-Bus and if the DMAC does not accept a bus control release request, bus operations cannot
be executed and, as a result, the pipeline stalls.
DMAC Internal Blocks
Snoop Function
Channel 3
Channel 2
Channel 1
Channel 0
31
Fig. 10.2 DMAC Internal Blocks
TMP19A44 (rev1.3) 10-3
Source address register (SARx)
Destination address register (DARx)
Byte count register (BSRx)
Channel control register (CCRx)
Channel status register (CSRx)
DMA transfer control register (DTCRx)
DMA control register (DCR)
Request select register (RSR)
Data holding register (DHR)
(x＝0~3)
0
TMP19A44
2010-04-01