tmp19a44fda TOSHIBA Semiconductor CORPORATION, tmp19a44fda Datasheet - Page 396

• Manufacturer Part Number: tmp19a44fda
• Description: 32bit Tx System Risc
• Manufacturer: TOSHIBA Semiconductor CORPORATION

Serial Channel (HSIO)
•
Example baud rate setting:
2)
1)
2)
I/O interface mode
Baud rate =
The highest baud rate will be generated when fsys is 80 MHz. If double buffering is used, the
divide ratio can be set to "2" and the resulting output baud rate will be 10 Mbps. (If double
buffering is not used, the highest baud rate will be 5 Mbps applying the divide ratio of "2.")
Division by an integer (divide by N):
Using the baud rate generator input clock sys, setting the divide ratio N
(HBR0CR<BR0S5:0>) = 4, and setting HBR0CR<BR0ADDE> = "0," the resulting baud rate
in the UART mode is calculated as follows:
* Clocking conditions
Baud rate =
= 80 × 10
(Note)
For divide by N + (16-K)/16 (only for UART mode):
Using the baud rate generator fsys, setting the divide ratio N (HBR0CR<BR3S5:0>) = 4,
setting K (HBR0ADD<BR3K3:0>) = 14, and selecting HBR0CR<BR3ADDE> = 1, the
resulting baud rate is calculated as follows:
* Clocking conditions
Baud rate =
= 80 × 10
6
6
/ (4 +
The divide by (N + (16-K)/16) function is inhibited and thus HBR0ADD
<BR0K3:0> is ignored.
/ 4 / 16 =1250 k (bps)
Frequency
fsys
4
4
+
(16
16
Fsys
2
/16
TMP19A44(rev1.3) 15-6
16
) / 16 = 121.2 k (bps)
−
14)
divided
System clock
High speed clock gear :
System clock
High-speed clock gear :
/16
fsys
by the
divide
ratio
:
:
/2
High-speed (fc)
x 1 (fc)
High-speed (fc)
x 1 (fc)
TMP19A44
2010-04-01