tmp19a44fda TOSHIBA Semiconductor CORPORATION, tmp19a44fda Datasheet - Page 602

• Manufacturer Part Number: tmp19a44fda
• Description: 32bit Tx System Risc
• Manufacturer: TOSHIBA Semiconductor CORPORATION

Flash Memory Operation
(3) Interface Specification
(4) Data Transfer Format
Both UART (asynchronous) and I/O Interface (synchronous) modes are supported. The communication
formats are shown below. In the subsections that follow, virtual addresses are indicated, unless
otherwise noted.
The host controller is to issue one of the commands listed in Table 24.4 to the target board. Table 24.6
illustrate the sequence of two-way communications that should occur in response to each command.
In Single Boot mode, an SIO channel is used for communications with a programming controller.
Power Supply Pins
Mode-Setting Pin
Reset Pin
Communication
Pins
•
•
UART mode
I/O Interface mode
Communication channel: SIO Channel 0 (SIO0)
Transfer mode:
Data length:
Parity bits:
STOP bits:
Baud rate:
Communication channel:
Transfer mode:
Synchronization clock (SCLK0): Input mode
Handshaking signal:
Baud rate:
Code
10H
Pin
Table 24.4 Single Boot Mode Commands
Table 24.3 Required Pin Connections
DVCC3
DVSS
TXD0 (P60)
RXD0 (P61)
SCLK0 (P62)
P63
BOOT
RESET
RAM Transfer
TMP19A44 (rev1.3)24-17
UART (asynchronous) mode, half-duplex, LSB first
8 bits
None
1
Arbitrary baud rate
UART Mode
Not Required
Not Required
SIO Channel 0 (SIO0)
I/O Interface mode, full-duplex, LSB first
P63 output mode
Arbitrary baud rate
Command
Required
Required
Required
Required
Required
Required
Interface
I/O Interface Mode
Required (Input Mode)
Required (OUTPUT
Required
Required
Required
Required
Required
Required
Mode)
TMP19A44
2010-04-01