tmp19a44fda TOSHIBA Semiconductor CORPORATION, tmp19a44fda Datasheet - Page 619

• Manufacturer Part Number: tmp19a44fda
• Description: 32bit Tx System Risc
• Manufacturer: TOSHIBA Semiconductor CORPORATION

Flash Memory Operation
Note:
8) Automatic erasing of protection bits
because the protection bits may not have been correctly programmed. If all the protection bits have
been programmed, the flash memory cannot be read from any area outside the flash memory such
as the internal RAM.
The protection condition can be canceled by the automatic protection bit erase operation. The
target bits are specified in the seventh bus write cycle and when the command is completed, the
device is in a condition all the blocks are erased. This operation can be checked by monitoring
FLCS <FlashBusy>. Also, you can check the protection condition by monitoring FLCS
<PROTECT 3:0>.
When the automatic protection bit erase command is command written, the flash memory is
automatically initialized within the device. When the seventh bus write cycle is completed, the
entire area of the flash memory data cells is erased and then the protection bits are erased. While
no automatic verify operation is performed internally to the device, be sure to read the data to
confirm that it has been correctly erased. For returning to the read mode while the automatic
operation after the seventh bus cycle is in progress, it is necessary to use the hardware reset to reset
the device. If this is done, it is necessary to check the status of protection bits by FLCS
<PROTECT 3:0> after retuning to the read mode and perform either the automatic protection bit
erase, automatic chip erase, or automatic block erase operation, as appropriate.
In any case, any new command sequence is not accepted while it is in an automatic operation to
erase protection bits. If it is desired to stop the operation, use the hardware reset function. When
the automatic operation to erase protection bits is normally terminated, it returns to the read mode.
The FLCS <FlashBusy> bit is "0" while in automatic operation and it turns to "1"
when the automatic operation is terminated.
Software reset is ineffective in the seventh bus write cycle of the automatic
protection bit programming command. The FLCS <FlashBusy> bit turns to "0"
after entering the seventh bus write cycle.
TMP19A44 (rev1.3)24-34
TMP19A44
2010-04-01