tmp19a44fda TOSHIBA Semiconductor CORPORATION, tmp19a44fda Datasheet - Page 56

• Manufacturer Part Number: tmp19a44fda
• Description: 32bit Tx System Risc
• Manufacturer: TOSHIBA Semiconductor CORPORATION

Exceptions/Interrupts
6.1.3.2
(Note) When a hardware interrupt and a software interrupt are detected simultaneously, a
(1) Priority
CPU executes an exception of an interrupt with the highest priority.
There are cases that multiple exceptions and interrupts are detected simultaneously. To handle the situation, the
The priority of the exceptions/ interrupts is shown below.
maskablehardware interrupt is executed.
Exceptions/ interrupts detection
Table 6.2 Exceptions/ interrupts priority (when detected simultaneously)
Priority
Higher
Lower
Exceptions/ interrupts
Reset exception
Single step exception
Non-maskable interrupt (NMI)
Hardware interrupts
Software interrupts
Address error exception (instruction fetch)
Bus error exception (instruction fetch/ store)
Debug breakpoint exception
Co-processor unusable exception
Reserved instruction exception
Integer overflow exception
Trap exception
System call exception
Breakpoint exception
Address error exception (load/store)
Bus error exception (data access)
TMP19A44(rev1.3) 6-6
TMP19A44
2010-04-01