tmp19a44fda TOSHIBA Semiconductor CORPORATION, tmp19a44fda Datasheet - Page 93

• Manufacturer Part Number: tmp19a44fda
• Description: 32bit Tx System Risc
• Manufacturer: TOSHIBA Semiconductor CORPORATION

Exceptions/Interrupts
6.5.2.8
(1) Preconfiguration
(2) Enabling Multiple Interrupts
(3) Returning from Multiple Interrupt
(4) Proper use of Status <EXL> and Status <IE>
Multiple Interrupts
is being processed. When an interrupt request is accepted, ILEV <CMASK> of INTC is automatically
updated to the interrupt level of the interrupt accepted. It enables an interrupt with the higher interrupt level
than the current one.
needed.
Clearing the bit to “0” enables an interrupt.
the interrupt is discontinued. Set Status<EXL> of the CP0 register to “1” to disable interrupts. It can prevent
a new interrupt from occurring before returning from the multiple interrupts. Otherwise, original interrupt
data may be destroyed.
Interrupts must be prohibited while saving the register contents described in (1) and returning from multiple
interrupts described in (3). Usually, interrupts can be prohibited with Status<EXL> controlled by hardware.
Status <IE> is used for other general interrupt enable/disable control functions.
interrupts. If not, these registers are overwritten by the second and subsequent interrupts.
In "multiple interrupts" processing, an interrupt with higher interrupt level is processed while an interrupt
To execute multiple interrupts, the contents in the following registers must be saved before enabling the
In addition to the registers shown above, save the contents of the HI, LO, Cause and Config registers if
When an interrupt is accepted, Status <EXL> of the CP0 register is set to "1" disabling further interrupts.
After returning from the multiple interrupts handler, the CPU restarts the suspended interrupt from where
Status<EXL> and Status<IE> control to enable or disable the multiple interrupts.
Status <EXL> is set to "1" upon interrupt generation and cleared to "0" by the ERET instruction.
The following describes how the multiple interrupts are handled.
●CP0 register
EPC
SSCR
Status
PC of the interrupt generated
Shadow register control
CPU status
TMP19A44(rev1.3) 6-43
TMP19A44
2010-04-01