tmp19a44fda TOSHIBA Semiconductor CORPORATION, tmp19a44fda Datasheet - Page 265

• Manufacturer Part Number: tmp19a44fda
• Description: 32bit Tx System Risc
• Manufacturer: TOSHIBA Semiconductor CORPORATION

(Note)
DMA Controller (DMAC)
10.2 Configuration
10.2.1
Request for bus control authority
In Fig. 10.1, signals indicated by * are internal signals.
Fig. 10.1 shows the internal connections with the DMAC in the TMP19A44.
The DMAC has eight DMA channels. Each of these channels handles the data transfer request signal
(INTDREOn) from the interrupt controller and the acknowledgment signal (DACKn) generated in
response to INTDREOn, where "n" is a channel number from 0 to 7. External pins (DREQ0 and
DREQ4) are internally wired to allow them to function as pins of the port F. To use them as pins of the
port F, they must be selected by setting the function control register PFFC to an appropriate setting.
Pins, DACK0 and DACK4, handle the data transfer request and acknowledge signal output supplied
through external pins, DREQ0 and DREQ4. Channel 0 is given higher priority than channel 1, channel
1 higher priority than channel 2 and channel 2 higher priority than channel 3. Subsequent channels are
given priority in the same manner.
The TX19A/ H1 processor core has a snoop function. Using the snoop function, the TX19A/ H1
processor core opens the core's data bus to the DMAC, thus allowing the DMAC to access the internal
ROM and RAM linked to the core. The DMAC is capable of determining whether or not to use this
snoop function. For further information on the snoop function, refer to 10.2.3 "Snoop Function."
Two types of bus control authority (SREQ and GREQ) are available to the DMAC and which type of
control right to use depends on the use or nonuse of the snoop function. GREQ is a request for bus
control authority if the DMAC does not use the snoop function, while SREQ is a request for bus control
authority if the DMAC uses the snoop function. SREQ is given higher priority than GREQ.
Notification of bus control
Notification to release
bus control authority
Request to release bus
processor core
authority ownership
Internal Connections of the TMP19A44
TX19A
control authority
Address
Contro
Data
Fig. 10.1 DMAC Connections in the TMP19A44
l
DREQ [4,0]
TMP19A44 (rev1.3) 10-2
Port function
control
DACK [4,0]
DMAC
INTDREQ [7 : 0]*
DACK [7 : 0]*
BUSGNT
(external request)
Interrupt controller
*
TMP19A44
External
interrupt
request
Internal I/O
interrupt
request
BUSREL *
BUSREQ *
HAVEIT *
2010-04-01