tmp19a44fda TOSHIBA Semiconductor CORPORATION, tmp19a44fda Datasheet - Page 307

• Manufacturer Part Number: tmp19a44fda
• Description: 32bit Tx System Risc
• Manufacturer: TOSHIBA Semiconductor CORPORATION

16-bit Timer/Event Counters (TMRBs)
11.3.2
11.3.3
This is the 16-bit binary counter that counts up in response to the input clock specified by
TB0MOD<TB0CLK1:0>.
UC0 input clock can be selected from either three types - φT1, φT4 and φT16 - of prescaler output clock
or the external clock of the TB0IN0 pin.
TB0RUN<TB0RUN> and if UC0 matches the TB0RG1 timer register, it is cleared to "0" if the setting
is "clear enable." Clear enable/disable is specified by TB0MOD<TB0CLE>.
If the setting is "clear disable," the counter operates as a free-running counter. T
the UC0 can be captured by reading the TB0U
If UC0 overflow occurs, the INTTB0 overflow interrupt is generated.
These are 16-bit registers for specifying counter values and two registers are built into each channel. If a
value set on this timer register matches that on a UC0 up-counter, the match detection signal of the
comparator becomes active.
To write data to the TB0RG0H/L and TB0RG1H/L timer registers, either a 2-byte data transfer
instruction or a 1-byte data transfer instruction written twice in the order of low-order 8 bits followed by
high-order 8 bits can be used.
TB0RG0 of this timer register is paired with register buffer 0 - a double-buffered configuration.
TB0RG0/1
TB0WBF
enabled, data is transferred from register buffer 0 to the TB0RG0/1 timer register when there is a match
between UC0 and TB0RG0/1.
A reset initializes
buffering, write data to the timer register, set
register buffers.
TB0RG0/1 and the register buffers are assigned to the same address:
<TB0WBF>
the value is only written to each register buffer. To write an initial value to the timer register, therefore,
the register buffers must be set to "disable."
Up-counter (UC0) and Time Up-counter Registers (TB0UC)
Timer Registers (TB0RG0, TB0RG1)
> = "0," double buffering is disabled and if <
uses
= "0," the same value is written to TB0RG0/1 and each register buffer; if
TB0CR<TB0WBF>
TB0CR <TB0WBF>
TMP19A44(rev1.3) 11-9
to control the enabling/disabling of double buffering so that if <
to "0" and sets double buffering to "disable." To use double
C registers.
<TB0WBF>
For UC0, start, stop and clear are specified by
TB0WBF
to "1" and then write the following data to the
> = "1," it is enabled. If double buffering is
0xFF00_4520/0xFF00_4524
TMP19A44
he current count value of
<TB0WBF>
2010-04-01
= "1,"
. If