tmp19a44fda TOSHIBA Semiconductor CORPORATION, tmp19a44fda Datasheet - Page 285

• Manufacturer Part Number: tmp19a44fda
• Description: 32bit Tx System Risc
• Manufacturer: TOSHIBA Semiconductor CORPORATION

DMA Controller (DMAC)
10.4.2
For the DMAC to transfer data, a transfer request must be issued to the DMAC. There are two types of
transfer request: an internal transfer request and an external transfer request. Either of these transfer
requests can be selected and specified for each channel.
Whichever is selected, the DMAC acquires bus control authority and starts to transfer data if the
transfer request is generated after the start of channel operation.
•
•
Internal transfer request
If the Str bit of CCR is set to "1" when the ExR bit of CCRn is "0," a transfer request is generated
immediately. This transfer request is called an internal transfer request.
The internal transfer request is valid until the channel operation is completed. Therefore, data can
be transferred continuously if either of two events shown below does not occur:
* A transition to a channel of higher priority
* A shift of bus control authority to another bus master of higher priority
External transfer request
If the ExR bit of CCRn is "1," setting the Str bit of CCR to "1" allows a channel to go into a
standby mode. The INTC or an external device then generates the INTDREQn or DREQn signal
for this channel to notify the DMAC of a transfer request, and a transfer request is generated. This
transfer request is called an external transfer request. The external transfer request is used for a
single and a continuous transfer.
The TMP19A44 recognizes the transfer request signal by detecting the "L" level of the
INTDREQn signal or by detecting the falling edge or "L" level of the DREQn signal.
The unit of data to be transferred in response to one transfer request is specified in the TrSiz field
of CCRn, and 32, 16 or 8 bits can be selected.
Transfer requests using INTDREQn and DREQn are described in detail on the next page.
Transfer Request
Example 2: Irregular decrease for a source device and monotonic decrease for a destination device
1st
2nd
3rd
4th
SAC: Address decrease
DAC: Address decrease
TrSiz: Transfer unit 16 bits
Source address: Initial value
Destination address:
SACM: 010 → counting to begin from bit 8 of the address counter
DACM: 000 → counting to begin from bit 0 of the address counter
0xA000_1000
0x9FFF_FF00
0x9FFF_FE00
0x9FFF_FD00
Source
TMP19A44 (rev1.3) 10-22
…
0xB000_0000
0xAFFF_FFFE
0xAFFF_FFFC
0xAFFF_FFFA
Destination
0xA000_1000
0xB000_0000
…
TMP19A44
2010-04-01