tmp19a44fda TOSHIBA Semiconductor CORPORATION, tmp19a44fda Datasheet - Page 270

• Manufacturer Part Number: tmp19a44fda
• Description: 32bit Tx System Risc
• Manufacturer: TOSHIBA Semiconductor CORPORATION

When software is reset, the CCRn,CSRn,SARn,DARn,DTCRn,DCR,RSR register is initialized.
The BCRn,DHR register is not initialized.
(Note 1) If a write to the DCR register occurs during a software reset right after the last round of DMA
(Note 2) An attempt to execute a write (software reset) to the DCR register by DMA transfer must be
DMA Controller (DMAC)
transfer is completed, the interrupt to stop DMA transfer is not canceled although the
channel register is initialized.
strictly avoided.
Bit
4
3
2
1
0
Mnemonic
Rst4
Rst3
Rst2
Rst1
Rst0
Fig. 10.3 DMA Control Register (DCR)
Reset 4
Reset 3
Reset 2
Reset 1
Reset 0
TMP19A44 (rev1.3) 10-7
Field name
Performs a software reset of the DMAC channel 4. If the
Rst4 bit is set to 1, internal registers of the DMAC channel 4
and a corresponding bit of the channel 4 of the RSR register
are reset to their initial values. The transfer request of the
channel 4 is canceled and the channel 4 goes into an idle
state.
0: Don't care
1: Initializes the DMAC channel 4
Performs a software reset of the DMAC channel 3. If the
Rst3 bit is set to 1, internal registers of the DMAC channel 3
and a corresponding bit of the channel 3 of the RSR register
are reset to their initial values. The transfer request of the
channel 3 is canceled and the channel 3 goes into an idle
state.
0: Don't care
1: Initializes the DMAC channel 3
Performs a software reset of the DMAC channel 2. If the
Rst2 bit is set to 1, internal registers of the DMAC channel 2
and a corresponding bit of the channel 2 of the RSR register
are reset to their initial values. The transfer request of the
channel 2 is canceled and the channel 2 goes into an idle
state.
0: Don't care
1: Initializes the DMAC channel 2
Performs a software reset of the DMAC channel 1. If the
Rst1 bit is set to 1, internal registers of the DMAC channel 1
and a corresponding bit of the channel 1 of the RSR register
are reset to their initial values. The transfer request of the
channel 1 is canceled and the channel 1 goes into an idle
state.
0: Don't care
1: Initializes the DMAC channel 1
Performs a software reset of the DMAC channel 0. If the
Rst0 bit is set to 1, internal registers of the DMAC channel 0
and a corresponding bit of the channel 0 of the RSR register
are reset to their initial values. The transfer request of the
channel 0 is canceled and the channel 0 goes into an idle
state.
0: Don't care
1: Initializes the DMAC channel 0
Description
TMP19A44
2010-04-01