tmp19a44fda TOSHIBA Semiconductor CORPORATION, tmp19a44fda Datasheet - Page 84

• Manufacturer Part Number: tmp19a44fda
• Description: 32bit Tx System Risc
• Manufacturer: TOSHIBA Semiconductor CORPORATION

Exceptions/Interrupts
(7) Configuring INTC
lower interrupt level than the level set in ILEV<CMASK> is suspended.
factor, write IVR of the interrupt you want to execute to the INTCLR register.
an interrupt level of each factor are configurable.
write “1” to ILEV<MLEV> at the same time when writing the level to ILEV<CMASK>.
With INTC, mask levels of the entire INTC, a base address of interrupt vector table and an active state and
An interrupt level to be detected by INTC can be set in the ILEV register. An interrupt factor with the
“0” is set as a default level. In this condition, all the interrupt levels can be detected. To change the level,
Set a base address of an interrupt vector table to IVR [31:9] of the IVR resister. Prepare the table in the
address configured.
Clear an interrupt factor already held in INTC to generate an interrupt in appropriate timing. To clear the
Set an active state and an interrupt level to IMC register with which the setting for each factor is available.
Some interrupt factors designate a certain active state. See the IMC register section for details.
Set “H” level when using an interrupt to clear standby mode.
Set “L” level when using software set.
●INTC register
ILEV<CMASK>
ILEV<MLEV>
●INTC register
IVR[31:9]
●INTC register
INTCLR<EICLR>
●INTC register
IMCn<EIMm>
IMCn<ILm>
TMP19A44(rev1.3) 6-34
←
←
←
←
←
←
Interrupt mask level
“1”
Interrupt handler base address
IVR
Active state
Interrupt level
TMP19A44
2010-04-01