tmp19a44fda TOSHIBA Semiconductor CORPORATION, tmp19a44fda Datasheet - Page 608

• Manufacturer Part Number: tmp19a44fda
• Description: 32bit Tx System Risc
• Manufacturer: TOSHIBA Semiconductor CORPORATION

Flash Memory Operation
15. If the (m+2)th byte was a normal acknowledge response, a branch is made to the address specified
by the 19th to 22nd bytes in 32-bit ISA mode.
series of the 19th to 24th bytes must result in zero (with the carry dropped). If it is not zero, one or
more bytes of data has been corrupted. In case of a checksum error, the RAM Transfer routine sends
back 11H to the controller and returns to the state in which it waits for a command (i.e., the 3rd byte)
again.
12. The 27th to mth bytes from the controller are stored in the on-chip RAM of the TMP19A44.
Storage begins at the address specified by the 19th–22nd bytes and continues for the number of bytes
specified by the 23rd–24th bytes.
13. The (m+1)th byte is a checksum value. To calculate the checksum value, add the 27th to mth bytes
together, drop the carries and take the two’s complement of the total sum. Transmit this checksum
value from the controller to the target board. The checksum calculation is described in details in Section
“Checksum Calculation
14. The (m+2)th byte is a acknowledge response to the 27th to (m+1)th bytes.
First, the RAM Transfer routine checks for a receive error in the 27th to (m+1)th bytes. If there was a
receive error, the RAM Transfer routine sends back 18H and returns to the state in which it waits for a
command (i.e., the 3rd byte) again. In this case, the upper four bits of the acknowledge response are the
same as those of the previously issued command (i.e., all 1s). When the SIO0 is configured for I/O
Interface mode, the RAM Transfer routine does not check for a receive error.
Next, the RAM Transfer routine performs the checksum operation to ensure data integrity. Adding the
series of the 27th to (m)th bytes must result in zero (with the carry dropped). If it is not zero, one or
more bytes of data has been corrupted. In case of a checksum error, the RAM Transfer routine sends
back 11H to the controller and returns to the state in which it waits for a command (i.e., the 3rd byte)
again. When the above checks have been successful, the RAM Transfer routine returns a normal
acknowledge response (10H) to the controller.
When the above checks have been successful, the RAM Transfer routine returns a normal
acknowledge response (10H) to the controller.
The RAM storage start address must be within the range 0xFFFF_A400–0xFFFF_FFFF.
“
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TMP19A44 (rev1.3)24-23
TMP19A44
2010-04-01