tmp19a44fda TOSHIBA Semiconductor CORPORATION, tmp19a44fda Datasheet - Page 245

• Manufacturer Part Number: tmp19a44fda
• Description: 32bit Tx System Risc
• Manufacturer: TOSHIBA Semiconductor CORPORATION

External Bus Interface
8.4 External Bus Operations (Multiplexed Bus Mode)
This section describes various bus timing values. The timing diagram shown below assumes that the address
buses are A23 through A16 and that the address/data buses are AD15 through AD0.
(1) Basic bus operation
CSn
The external bus cycle of the TMP19A44 basically consists of three clock pulses and a wait can be inserted
as mentioned later. The basic clock of an external bus cycle is the same as the internal system clock.
Fig. 8.11 shows read bus timing and Fig. 8.12 shows write bus timing. If internal areas are accessed,
address buses remain unchanged and the ALE does not output latch pulse as shown in these figures.
Additionally, address/data buses are in a state of high impedance and control signals such as RD and
do not become active.
A [23:16]
AD [15:0]
ALE
RD
CSn
A [23:16]
AD [15:0]
ALE
WR
Fig. 8.11 Read Operation Timing Diagram
Fig. 8.12 Write Operation Timing Diagram
tsys
ADR
TMP19A44 (rev1.3) 8-17
ADR
External access
tsys
External area
DATA
DATA
Higher-order address HOLD
Higher-order address HOLD
No output of RD
Output Hi − Z
No output of ALE
Internal access
Internal area
No output of WR
No output of ALE
Output Hi − Z
TMP19A44
2010-04-01
WR