tmp19a44fda TOSHIBA Semiconductor CORPORATION, tmp19a44fda Datasheet - Page 92

• Manufacturer Part Number: tmp19a44fda
• Description: 32bit Tx System Risc
• Manufacturer: TOSHIBA Semiconductor CORPORATION

Exceptions/Interrupts
(2) Clearing interrupt request (INTC)
(3) Branch to Interrupt Handler
(4) Clearing Interrupt Factor
(6) Returning from Exception Handler
(5) Interrupt Handler Processing
setting a value of IVR[8:0] to INTCLR register.
CPU.
interrupts are prohibited. The setting to use multiple interrupts is described in ”6.6.2.7Multiple Interrupts”.
values specified in IVR [31:0] can be used as the start address. The CPU branches off to the address.
factor is required.
IVR to the INTCLR register. When the next valid edge is detected, a new factor is recognized. See (2)
Clearing interrupt request (INTC).
general purpose register and CP0 register, which may be rewritten by general interrupts, even if multiple
interrupts are not used.
enabled (SSCR<SSD> of the CP0 register is “0”), contents in the general purpose register except for r26,
r27, r28 and r29（Shadow Register Set Number 1~7） are automatically saved. Save by the user program
is not needed.
By the signal from the CPU, INTC fixes a request level. INTC clears the request sent to the CPU by
Upon clearing the request, an interrupt with the highest priority that suspended in INTC is requested to the
When the CPU branches off to the exception handler, “1” is set to the Status<EXL> bit, and next
If the start address of the interrupt handler table is set in IVR [31:9] of the interrupt controller register, the
As for an interrupt detected by a level, an interrupt request exists unless the factor is cleared. Clearing the
As for an interrupt detected by an edge, an interrupt factor is cleared by setting the corresponding interrupt
Usually an interrupt handler save the required register and handles interrupts. If the shadow register set is
Save the contents of the Status, EPC, SSCR, HI, LO, Cause and Config registers, if needed.
General exceptions are acceptable if interrupts are prohibited. We recommend saving the contents of the
See “6.1.3.6 Returning from Exception/ Interrupts”.
●INTC
INTCLR[8:0]
Value of IVR[8:0] according to factor
(See factor list)
TMP19A44(rev1.3) 6-42
TMP19A44
2010-04-01