tmp19a44fda TOSHIBA Semiconductor CORPORATION, tmp19a44fda Datasheet - Page 283

• Manufacturer Part Number: tmp19a44fda
• Description: 32bit Tx System Risc
• Manufacturer: TOSHIBA Semiconductor CORPORATION

DMA Controller (DMAC)
(3) Transfer request modes
(4) Address mode
(5) Channel operation
Two transfer request modes are used for the DMAC: an internal transfer request mode and an
external transfer request mode.
In the internal transfer request mode, a transfer request is generated inside the DMAC. Setting a
start bit (Str bit of the channel control register CCRn) in the internal register of the DMAC to "1"
generates a transfer request, and the DMAC starts to transfer data.
In the external transfer request mode, after a start bit is set to "1," a transfer request is generated
when a transfer request signal INTDREQn output by the INTC is input, or when a transfer request
signal DREQn output by an external device is input. For the DMAC, two modes are provided: the
level mode in which a transfer request is generated when the "L" level of the INTDREQn signal is
detected and a mode in which a transfer request is generated when the falling edge or "L" level of
the DREQn signal is detected.
For the DMAC of the TMP19A44, only one address mode is provided: a dual address mode. A
single address mode is not available.
In the dual address mode, both single and continuous transfers are available. Source and
destination device addresses are output by the DMAC. To access an I/O device, the DMAC asserts
the DACKn signal. In the dual address mode, two bus operations, a read and a write, are executed.
Data that is read from a source device for transfer is first put into the data holding register (DHR)
inside the DMAC and then written to a destination device.
The DMAC has eight channels (channels 0 through 7). A channel is activated and put into a
standby mode by setting a start (Str) bit in the channel control register (CCRn) to "1."
If a transfer request is generated when a channel is in a standby mode, the DMAC acquires bus
control authority and transfers data. If there is no transfer request, the DMAC releases bus control
authority and goes into a standby mode. If data transfer has been completed, a channel is put in an
idle state. Data transfer is completed either normally or abnormally (e.g. occurrence of errors). An
interrupt signal can be generated upon completion of data transfer.
Fig. 10.12 shows the state transitions of channel operation.
Idle
Fig. 10.12 Channel Operation State Transition
Bus control authority not acquired
TMP19A44 (rev1.3) 10-20
completed
Transfer
Start
Transfer
Wait
Bus control authority acquired
Bus control authority acquired
Bus control authority not acquired
TMP19A44
2010-04-01