tmp19a44fda TOSHIBA Semiconductor CORPORATION, tmp19a44fda Datasheet - Page 249

• Manufacturer Part Number: tmp19a44fda
• Description: 32bit Tx System Risc
• Manufacturer: TOSHIBA Semiconductor CORPORATION

External Bus Interface
ALE (ALESEL = 0)
AD [15:0]
(ALESEL = 1)
AD [15:0]
(3) Time that it takes before ALE is asserted
When the ALE is 1 clock or 2 clocks
One of system clocks of 1 to 4 can be selected as the time that it takes before ALE is asserted. The setting
bit is located in the system clock control register. The default is 2 clocks. This assert setting cannot be
established for each block in an external area and the same setting is commonly used in an external address
space.
Fig. 8.16 shows the timing when the ALE is 1 clock or 2 clocks.
Fig. 8.16 Read Operation Timing Diagram (When the ALE is 1 Clock or 2 Clocks)
fsys
A[23:16]
AD[15:0]
ALE
/RD
Fig. 8.15 Time That It Takes Before ALE Is Asserted
Lower-order address
tsys
Higher-order address
TMP19A44 (rev1.3) 8-21
tsys
Data
1 clock
2 clocks
Higher-order address
TMP19A44
Data
2010-04-01