tmp19a44fda TOSHIBA Semiconductor CORPORATION, tmp19a44fda Datasheet - Page 605

• Manufacturer Part Number: tmp19a44fda
• Description: 32bit Tx System Risc
• Manufacturer: TOSHIBA Semiconductor CORPORATION

1)
Flash Memory Operation
(6) Overview of the Boot Program Commands
RAM Transfer Command (see Table 24.6)
program offers these four commands, the details of which are provided on the subsections 1) through 4).
1.
description of how the serial operation mode is determined, see Section 0. If it is determined as UART
mode, the boot program then checks if the SIO0 is programmable to the baud rate at which the 1st byte
was transferred. During the first-byte interval, the RXE bit in the SC0MOD0 register is cleared.
When Single Boot mode is selected, the boot program is automatically executed on startup. The boot
The 1st byte specifies which one of the two serial operation modes is used. For a detailed
1. RAM Transfer command
• To communicate in UART mode
• To communicate in I/O Interface mode
The RAM Transfer command stores program code transferred from a host controller to the on-
chip RAM and executes the program once the transfer is successfully completed. The
maximum program size is 24 Kbytes. The RAM storage start address must be within the range.
The RAM Transfer command can be used to download a flash programming routine of your
own; this provides the ability to control on-board programming of the flash memory in a
unique manner. The programming routine must utilize the flash memory command sequences
described in Section 24.3.
Before initiating a transfer, the RAM Transfer command checks a password sequence coming
from the controller against that stored in the flash memory. If they do not match, the RAM
Transfer command aborts.
Once the RAM Transfer command is complete, the whole on-chip RAM is accessible.
Send, from the controller to the target board, 86H in UART data format at the desired baud rate.
If the serial operation mode is determined as UART, then the boot program checks if the SIO0
can be programmed to the baud rate at which the first byte was transferred. If that baud rate is
not possible, the boot program aborts, disabling any subsequent communications.
Send, from the controller to the target board, 30H in I/O Interface data format at 1/16 of the
desired baud rate. Also send the 2nd byte at the same baud rate. Then send all subsequent bytes
at a rate equal to the desired baud rate.
In I/O Interface mode, the CPU sees the serial receive pin as if it were a general input port in
monitoring its logic transitions. If the baud rate of the incoming data is high or the chip’s
operating frequency is high, the CPU may not be able to keep up with the speed of logic
transitions. To prevent such situations, the 1st and 2nd bytes must be transferred at 1/16 of the
desired baud rate; then the boot program calculates 16 times that as the desired baud rate.
When the serial operation mode is determined as I/O Interface mode, the SIO0 is configured
for SCLK Input mode. Beginning with the third byte, the controller must ensure that its AC
timing restrictions are satisfied at the selected baud rate. In the case of I/O Interface mode, the
boot program does not check the receive error flag; thus there is no such thing as error
acknowledge (x8H).
TMP19A44 (rev1.3)24-20
TMP19A44
2010-04-01