tmp19a44fda TOSHIBA Semiconductor CORPORATION, tmp19a44fda Datasheet - Page 445

• Manufacturer Part Number: tmp19a44fda
• Description: 32bit Tx System Risc
• Manufacturer: TOSHIBA Semiconductor CORPORATION

Serial Bus Interface (SBI)
Example: When the received slave address matches the SBI's own address and the direction bit is "1" in the
INTS0 interrupt
slave receiver mode
Slave mode (<MST> = "0")
In the slave mode, the SBI generates the INTS0 interrupt request on four occasions: 1) when the
SBI has received any slave address from the master, 2) when the SBI has received a general-call
address, 3) when the received slave address matches its own address, and 4) when a data transfer
has been completed in response to a general-call. Also, if the SBI loses arbitration in the master
mode, it switches to the slave mode. Upon the completion of data word transfer in which
arbitration is lost, the INTS0 interrupt request is generated, <PIN> is cleared to "0," and the SCL
pin is pulled to the "L" level. When data is written to or read from SBIDBR or when <PIN> is set
to "1," the SCL pin is released after a period of t
In the slave mode, the normal slave mode processing or the processing as a result of lost arbitration
is carried out.
SBISR <AL>, <TRX>, <AAS> and <AD0> are tested to determine the processing required. Table
16.2 shows the slave mode states and required processing.
(Note) X: Don't care
if TRX = 0
Then go to other processing
if AL = 1
Then go to other processing
if AAS = 0
Then go to other processing
SBICR1
SBIDBR
← X X X 1 0 X X X
← X X X X 0 X X X
TMP19A44 (rev1.3) 16-21
Sets the number of bits to be transmitted.
Sets the transmit data.
LOW
.
TMP19A44
2010-04-01