tmp19a44fda TOSHIBA Semiconductor CORPORATION, tmp19a44fda Datasheet - Page 290

• Manufacturer Part Number: tmp19a44fda
• Description: 32bit Tx System Risc
• Manufacturer: TOSHIBA Semiconductor CORPORATION

(Note)
(Note)
DMA Controller (DMAC)
If the DMAC operation has been completed abnormally due to a bus error, BCR, SAR and
DAR values cannot be guaranteed. If a bus error persists, refer to 21. "List of Functional
Registers" which appear later in this document.
10.4.5
The DMA transfer completion interrupt comes in two types: INTDMA0 for 0ch through 3ch
and INTDMA1 for 4ch through 7ch.
Concerning the four channels of the DMAC, the smaller the channel number assigned to each channel,
the higher the priority. If a transfer request is generated to channels 0 and 1 simultaneously, a transfer
request for channel 0 is processed with higher priority and the transfer operation is performed
accordingly. When the transfer request for channel 0 is cleared, the transfer operation for channel 1 is
performed if the transfer request still exists (An internal transfer request is retained if it is not cleared.
The interrupt controller retains an external transfer request if the active state for an interrupt request
assigned to DMA requests in the interrupt controller is set to edge mode. However, the interrupt
controller does not retain an external transfer request if the active state is set to level mode. If the active
state for an interrupt request assigned to DMA requests in the interrupt controller is set to level mode, it
is necessary to continue asserting the interrupt request signal).
If a transfer request is generated when data is being transferred through channel 1, a channel transition
occurs at channel 0, that is, data transfer through channel 1 is temporarily suspended and data transfer
through channel 0 is started. When the transfer request for channel 0 is cleared, data transfer through
channel 1 resumes.
Channel transitions occur upon the completion of data transfers (when the writing of all data in the
DHR has been completed).
Interrupts
•
Upon completion of a channel operation, the DMAC can generate interrupt requests ( INTDMAn :
DMA transfer completion interrupt) to the TX19A/ H1 processor core with two types of interrupts
available: a normal completion interrupt and an abnormal completion interrupt.
•
•
Order of Priority of Channels
INTDMA : 0ch,
INTDMA : 4ch,
Completion due to a bus error
−
Normal completion interrupt
If a channel operation is completed normally, the NC bit of CSRn is set to "1." If a normal
completion interrupt is authorized for the NIEn bit of the CCRn, the DMAC requests the
TX19A/ H1 processor core to authorize an interrupt.
Abnormal completion interrupt
If a channel operation is completed abnormally, the AbC bit of CSRn is set to "1." If an
abnormal completion interrupt is authorized for the AbIEn bit of the CCRn, the DMAC
requests the TX19A/ H1 processor core to authorize an interrupt.
If the DMAC operation has been completed abnormally due to a bus error, the AbC bit of
CSRn is set to "1" and the BES or BED bit of CSRn is set to "1."
A bus error was detected during data transfer.
0
4
INTDMA : 1ch,
INTDMA : 5ch,
TMP19A44 (rev1.3) 10-27
1
5
INTDMA : 2ch,
INTDMA : 6ch,
2
6
INTDMA : 3ch
INTDMA : 7ch
3
7
TMP19A44
2010-04-01