tmp19a44fda TOSHIBA Semiconductor CORPORATION, tmp19a44fda Datasheet - Page 664

• Manufacturer Part Number: tmp19a44fda
• Description: 32bit Tx System Risc
• Manufacturer: TOSHIBA Semiconductor CORPORATION

Electrical Characteristics
SCK Output Mode/
Active-Low SCK
OUTPUT DATA
27.9 High Speed Serial Channel Timing
SCL Input Mod
* HSCLK rise or fall: Measured relative to the programmed active edge of HSCLK.
Active-High
HSCLK period
HSCLK Clock High width(input)
HSCLK Clock Low width (input)
TxD data to HSCLK rise or fall*
TxD data hold after HSCLK rise or fall*
RxD data valid to HSCLK rise or fall*
RxD data hold after HSCLK rise or fall*
HSCLK period
TxD data to HSCLK rise or fall*
TxD data hold after HSCLK rise or fall*
RxD data valid to HSCLK rise or fall*
RxD data hold after HSCLK rise or fall*
Input Mode
INPUT DATA
SCLK
SCLK
(1) I/O Interface mode（DVCC3=2.7V to 3.6V）
RxD
TxD
In the table below, the letter x represents the fsys cycle period, which varies depending on the
programming of the clock gear function.
1) HSCLK input mode（HSIO0 to HSIO2）
2) HSCLK output mode （HSIO0 to HSIO2）
Parameter
Parameter
t
t
OSS
SRD
VALID
0
t
0
SCY
tSCY
TscH
TscL
tOSS
tOHS
tSRD
tHSR
tSCY
tOSS
tOHS
tSRD
tHSR
TMP19A44 (rev1.3) 27-24
Sym
Sym
bol
bol
4
(tSCY /2) -10
(tSCY /2) -10
45
0
t
t
SCY
SCY
x/2 + 30
/2 - 3x – 45
/2 - 3x – 36
t
t
t
SCY
SCY
SCY
Min
Min
VALID
30
8x
1
Equation
Equation
1
/2
/2
/2
t
HSR
t
OHS
Max
Max
100
40
40
45
0
36.25
-32.5
-23.5
40/ 80 MHz
Min
100
Min
VALID
50
50
50
30
2
40 MHz
2
Max
Max
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
TMP19A44
Unit
Unit
VALID
3
3
2010-04-01