tmp19a44fda TOSHIBA Semiconductor CORPORATION, tmp19a44fda Datasheet - Page 288

• Manufacturer Part Number: tmp19a44fda
• Description: 32bit Tx System Risc
• Manufacturer: TOSHIBA Semiconductor CORPORATION

TMP19A44
10.4.3
Address Mode
In the address mode, whether the DMAC executes data transfers by outputting addresses to both source
and destination devices or it does by outputting addresses to either a source device or a destination
device is specified. The former is called the dual address mode, and the latter is called the single address
mode. For TMP19A44 only the dual address mode is available.
In the dual address mode, The DMAC first performs a read of the source device by storing the data
output by the source device in one of its registers (DHR). It then executes a write on the destination
device by writing the stored data to the device, thereby completing the data transfer.
DMAC
Source device
Address
Address bus
Data
Data bus
Destination device
Fig. 10.15 Basic Concept of Data Transfer in the Dual Address Mode
The unit of data to be transferred by the DMAC is the amount of data (32, 16 or 8 bits) specified in the
TrSiz field of the CCRn. One unit of data is transferred each time a transfer request is acknowledged.
In the dual address mode, the unit of data is read from the source device, put into the DHR and written
to the destination device.
Access to memory takes place when the specified unit of data is transferred. If access to external
memory takes place, 16-bit access takes place twice if the unit of data is set to 32 bits and if the bus
width set in the CS wait controller is 16 bits. Likewise, if the unit of data is set to 32 bits and if the bus
width set in the CS wait controller is 8 bits, 8-bit access takes place four times.
DMA Controller (DMAC)
TMP19A44 (rev1.3) 10-25
2010-04-01