tmp19a44fda TOSHIBA Semiconductor CORPORATION, tmp19a44fda Datasheet - Page 85

• Manufacturer Part Number: tmp19a44fda
• Description: 32bit Tx System Risc
• Manufacturer: TOSHIBA Semiconductor CORPORATION

Exceptions/Interrupts
6.5.2.3
(8) Enabling interrupt by CPU
Detection by CG
high-speed processing.
active state specified in the clock generator, and notified to INTC.
generator after detection. However, if a signal in “H” or “L” level is specified as the trigger to enter the
active state, the CPU considers that the interrupt factor is cleared upon exiting from the active state.
Therefore, the active state needs to be kept until the interrupt is detected.
need to set INTC so that the interrupt to clear standby is activated by a “H” signal.
Enable the interrupt by the CPU.
Set Status<IE> to “1”.
The following shows how to make IE bit “1”.
You can select one of them. We recommend No. 2 and No. 4 that prevent code increase and enable
If the interrupt is used for clearing the standby mode, the interrupt factor is detected by a trigger for an
The interrupt factor that enters active state triggered by a rising or falling edge is held in the clock
The interrupt detected by the clock generator is notified to INTC with a signal in “H” level. Therefore, you
1.
2.
3.
4.
●CPU register
Status<IE>
Set “1” to the Status<IE> bit of the CP0 register by 32 bit ISA MTC0 instruction.
Set a value other than “0” to the IER bit of the CP0 register by 32 bit ISA MTC0 instruction.
Set “1” to the Status<IE> bit of the CP0 register by 16 bit ISA MTC0 instruction.
Execute 16 bit ISA EI instruction.
TMP19A44(rev1.3) 6-35
←
“1”
TMP19A44
2010-04-01