tmp19a44fda TOSHIBA Semiconductor CORPORATION, tmp19a44fda Datasheet - Page 69

• Manufacturer Part Number: tmp19a44fda
• Description: 32bit Tx System Risc
• Manufacturer: TOSHIBA Semiconductor CORPORATION

Exceptions/Interrupts
6.4.1.3
6.4.1.4
6.4.1.5
Reading IVR Register
Clearing Factors
Return from Exception Handler
Status<EXL> of the CP0 register is set to “1”. Therefore, another software interrupt is not generated. A
software interrupt is recognized again if Status<EXL> is cleared to “0” when EXL bit is rewritten during
exception handling or returning from exception handler by ERET.
Status<IE> is a bit to enable both software and hardware interrupts. Clearing this bit to “0” disables both
interrupts.
read, no hardware interrupt from INTC is accepted.
A software interrupt factor is held unless the register settings are rewritten. In the exception handler,
To clear a software interrupt factor, clear one of the Status<IM>, Cause<IP> and Status<IE> bits to “0”.
Read the IVR register of INTC after a software interrupt is generated. “4” can be read. Until the IVR is
See “6.1.3.6 Returning from Exception/ Interrupts”.
TMP19A44(rev1.3) 6-19
TMP19A44
2010-04-01