tmp19a44fda TOSHIBA Semiconductor CORPORATION, tmp19a44fda Datasheet - Page 423

• Manufacturer Part Number: tmp19a44fda
• Description: 32bit Tx System Risc
• Manufacturer: TOSHIBA Semiconductor CORPORATION

Serial Channel (HSIO)
15.4 Operation of Each Circuit (Channel 0)
15.4.1 Serial Clock Generation Block
As channels 0 to 3 operate identically, only channel 0 is described here.
15.4.1.1
HSC0MOD0<SM1:0>
I/O interface mode
Serial clock is determined according to mode and register setting specified.
Specify mode in the mode control register 0 (HSC0MOD0<SM1:0>).
To use I/O interface mode, clock is specified in the control register HC0CR.
To use UART mode, clock is specified in the mode control register0 (HSC0MOD0<SC1:0>).
Table 15.4 and Table 15.5 show details of clock selection in I/O interface mode and UART mode
respectively.
This block generates basic transmit and receive clocks.
In this block, clock is determined according to baud rate generator and specified mode and register
setting.
Mode
Clock Selection Circuit
HSC0MOD0<SM1:0>
Table 15.4 Clock selection in I/O interface mode
UART mode
Table 15.5 Clock selection in UART mode
Mode
HC0CR<IOC>
HSCLK output
HSCLK input
Input/ output
selection
TMP19A44(rev1.3) 15-33
(Fixed to rising edge)
Clock edge selection
HC0CR<HSCLKS>
HSC0MOD0<SC1:0>
Clock selection
Falling edge
Rising edge
HSCLK input
Timer output
fsys/2
‐
fsys
Baud
Rising edge of HSCLK
input
Falling edge of HSCLK
input
output divided by 2
TMP19A44
Clock selection
rate
2010-04-01
generator