tmp19a44fda TOSHIBA Semiconductor CORPORATION, tmp19a44fda Datasheet - Page 86

• Manufacturer Part Number: tmp19a44fda
• Description: 32bit Tx System Risc
• Manufacturer: TOSHIBA Semiconductor CORPORATION

Exceptions/Interrupts
6.5.2.4
Interrupt
signal
Detection by INTC
(1) INTC detects interrupts according to active state specified per factor. An interrupt factor with the highest
(2) INTC compares the interrupt level of the selected factor with the level specified in the ILEV<CMASK>.
(3) When the CPU detects the interrupt, it sends a signal, which indicates the interrupt is accepted, to INTC.
(4) After receiving the signal, INTC sets the IVR to the IVR register and the interrupt level to the CMASK of
(5) INTC holds the information of the interrupt detected until the IVR is read. An interrupt factor with the
A factor, of which active state is rising or falling edge, is kept in the INTC after its detection. A factor, of
which active state is “H” or “L” level, is considered to be cleared if its level is changed from the active
state. Keep its active state until an interrupt is detected.
INTC handles an interrupt in the following procedure.
priority of the interrupt level and interrupt number is selected.
If the selected factor has the higher interrupt level, INTC notifies the CPU of the interrupt level.
If an interrupt with the higher priority is detected before the CPU sends the signal, an interrupt level is
replaced by it.
the ILEV register.
higher priority is suspended.
Level is fixed by interrupt
acceptance signal and
released by reading IVR.
…
(1)Priority
judgment
Level
TMP19A44(rev1.3) 6-36
IVR
(2) Comparison
Level>CMASK？
CMASK
(3)
notification
IVR
(5)
Level
(4)Interrupt
acceptance
TMP19A44
CPU
2010-04-01