tmp19a44fda TOSHIBA Semiconductor CORPORATION, tmp19a44fda Datasheet - Page 42

• Manufacturer Part Number: tmp19a44fda
• Description: 32bit Tx System Risc
• Manufacturer: TOSHIBA Semiconductor CORPORATION

Clock/Standby Control
5.5 Prescaler Clock Controller
5.6 Clock Multiplication Circuit (PLL)
5.4.4 Reducing the Oscillator Driving Capability
dissipation of the oscillator when it is connected to the oscillator connection pin.
capability).
capability (high capability). This is automatically set to the high driving capability state (<DRVOSCH> ="0")
whenever the oscillator starts oscillation due to mode transition.
to be input to each prescaler is obtained by selecting the "fperiph" clock at the SYSCR1<FPSEL> and then dividing
the clock according to the setting of SYSCR1<PRCK2:0>. After the controller is reset, fperiph/2 is selected as φT0.
lowers the oscillator input frequency while increasing the internal clock speed.
This function is intended for restricting oscillation noise generated from the oscillator and reducing the power
Setting the OSCCR1<DRVOSCH> to "1" reduces the driving capability of the high-speed oscillator (low
This is reset to the default setting "0." When the power is turned on, oscillation starts with the normal driving
Each internal I/O (TMRB0-11, SIO0-2, HSIO0-2 and SBI0) has a prescaler for dividing a clock. The clock φT0
This circuit outputs the fpll clock that is multiplied by eight of the high-speed oscillator output clock, fosc. This
Reducing the driving capability of the high-speed oscillator
C1
C2
Oscillator
Fig. 5.4 Oscillator Driving Capability
X1 pin
X2 pin
TMP19A44(rev1.3) 5-13
Enable oscillation
OSCCR1<DRVOSCH>
f
OSC
TMP19A44
2010-04-01