tmp19a44fda TOSHIBA Semiconductor CORPORATION, tmp19a44fda Datasheet - Page 355

• Manufacturer Part Number: tmp19a44fda
• Description: 32bit Tx System Risc
• Manufacturer: TOSHIBA Semiconductor CORPORATION

Serial Channel (SIO)
SCLK0 output
(shares P62)
SCLK0 input
(shares P62)
RXD0
(shares P61)
14.2 Block Diagram (Channel 0)
Fig. 14.2 shows the block diagram of SIO0.
Each channel consists of a prescaler, a serial clock generation circuit, a receive buffer and its control circuit, and
a send buffer and its control circuit. Each channel functions independently.
f
SYS
φT0
/2
FIFO control
SC0MOD0
<RXE>
φT1
φT4
φT16
φT64
RB8
I/O interface mode
Serial clock generation circuit
RXDCLK
<BR0CK1, 0>
φT1
Receive buffer 1 (shift register)
BR0CR
2
Receive counter
Receive buffer 2 (SC0BUF)
Receive control
(Φ16 only with
Internal data bus
4
<BR0S3:0>
UART)
φT4
Prescaler
BR0CR
8
Baud rate
generator
16 32 64
<BR0ADDE>
φT16
BR0CR
SC0MOD0
<WU>
<OERR><PERR><FERR>
Fig. 14.2 SIO0 Block Diagram
φ T64
<BR0K3:0>
128
BR0ADD
TMP19A44(rev1.3) 14-3
<PE>
Parity control
SC0CR
Error flag
÷ 2
SC0CR
interrupt control
<EVEN>
(from TMRB0)
channel
Serial
TB0OUT
SC0MOD0
<SC1, 0>
SC0CR
<IOC>
Internal data bus
I/O interface mode
UART
Mode
SC0MOD0
<SM1, 0>
TXDCLK
TB8
Send buffer 1 (shift register)
Transmit counter
(Φ16 only with
Send buffer 2 (SC0BUF)
Internal data bus
UART)
SIOCLK
Transmit
control
FIFO control
TMP19A44
SC0MOD0
<CTSE>
Interrupt request
(INTRX0)
Interrupt request
(INTTX0)
2010-04-01
(shares P62)
TXD0
(shares P60)
CTS
0