tmp19a44fda TOSHIBA Semiconductor CORPORATION, tmp19a44fda Datasheet - Page 68

• Manufacturer Part Number: tmp19a44fda
• Description: 32bit Tx System Risc
• Manufacturer: TOSHIBA Semiconductor CORPORATION

Exceptions/Interrupts
6.4.1.1
6.4.1.2
6.4 Software Interrupt
6.4.1 Factors
and use the same exception handler.
Software interrupt, which has two factors, occurs by setting the CP0 register.
A software interrupt has the same priority as a hardware interrupt. These interrupts may occur simultaneously
Condition of Generating Interrupt
Condition of not Generating Interrupt
register. At least 3 clocks are required to generate the interrupt after the factor is generated.
is “0”, IP must be “0”.
following conditions. The factor is suspended until the condition is changed as interrupt-acceptable.
A software interrupt factor is recognized when the following three settings are configured in the CP0
1) Status<IM>[1:0] (interrupt mask) is “1”.
2) Cause<IP>[1:0] (interrupt request) is “1”.
3) Status<IE> (interrupt enable bit) is “1”.
The Status<IM>[1:0] and Cause<IP>[1:0] need to be used together. If IM is “1”, IP must be “1”, and if IM
IE bit is to enable an interrupt and used for both software and hardware interrupts.
Even if the three settings shown above are completed, a software interrupt cannot be generated under the
・Status<ERL> or Status<EXL> bit is set
・In debug mode
・The CPU is stalled
Status<ERL> bit is set to “1” when reset or NMI occurs. Status<EXL> bit is set to “1” when an
interrupt or a general exception other than reset / NMI occurs. After an exception or an interrupt is
generated, software interrupts are prohibited.
Both Status<ERL> and Status<EXL> bits are rewritable. Writing these bits to “0”using exception
handler program enables software interrupts. These bits automatically return to “0” when returning
from exception handler by ERET instruction.
In debug mode, which is defined as duration from debug exception generation to returning by DRET
instruction, a software interrupt is ignored.
When the CPU is stalled for any reason, a software interrupt is not generated.
TMP19A44(rev1.3) 6-18
TMP19A44
2010-04-01