tmp19a44fda TOSHIBA Semiconductor CORPORATION, tmp19a44fda Datasheet - Page 376

• Manufacturer Part Number: tmp19a44fda
• Description: 32bit Tx System Risc
• Manufacturer: TOSHIBA Semiconductor CORPORATION

Serial Channel (SIO)
SC0MOD1
14.3.2.5
<I2S0>:
<FDPX1:0>:
<TXE>:
<SINT2:0>:
(Note)
bit Symbol
Read/Write
After reset
Enable <TXE> bit after setting other bits.
Mode Control Register 1
Function
Configures the transfer mode in the I/O interface mode. Also configures the FIFO if it is
enabled. In the UART mode, it is used only to specify the FIFO configuration.
transmission is in progress, transmission is inhibited only after the current frame of data is
completed for transmission.
(invalid for other modes).
Specifies the interval time of continuous transmission when double buffering or FIFO is
enabled in the I/O interface mode.
Specifies the IDLE mode operation.
This bit enables transmission and is valid for all the transfer modes. (Note) If disabled while
This parameter is valid for I/O interface mode when a clock is not input from SCLK0 pin
IDLE
0: Stop
1: Start
I2S0
R/W
7
0
Transfer mode setting
00: Transfer prohibited
01: Half duplex (RX)
10: Half duplex (TX)
11: Full duplex
FDPX1
TMP19A44(rev1.3) 14-24
R/W
6
0
FDPX0
R/W
5
0
Transmit
control
0: Disable
1: Enable
TXE
R/W
4
0
Interval time of continuous
transmission (for I/O interface)
000: None 100: 8SCLK
001: 1SCLK
010: 2SCLK
011: 4SCLK
SINT2
R/W
3
0
SINT1
R/W
101:16SCLK
110: 32SCLK
111: 64SCLK
2
0
TMP19A44
SINT0
R/W
1
0
2010-04-01
Write "0."
R/W
－
0
0