tmp19a44fda TOSHIBA Semiconductor CORPORATION, tmp19a44fda Datasheet - Page 389

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tmp19a44fda

Manufacturer Part Number
tmp19a44fda
Description
32bit Tx System Risc
Manufacturer
TOSHIBA Semiconductor CORPORATION
Datasheet

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Serial Channel (SIO)
14.4.2 Serial Clock Generation Block
14.4.2.1
SC0MOD0<SM1:0>
I/O interface mode
Serial clock is determined according to mode and register setting specified.
Specify mode in the mode control register 0 (SC0MOD0<SM1:0>).
To use I/O interface mode, clock is specified in the control register SC0CR.
To use UART mode, clock is specified in the mode control register0 (SC0MOD0<SC1:0>).
Table 14. and Table 14. show details of clock selection in I/O interface mode and UART mode respectively.
This block generates basic transmit and receive clocks.
In this block, clock is determined according to baud rate generator and specified mode and register
setting.
Mode
Clock Selection Circuit
SC0MOD0<SM1:0>
Table 14.7 Clock selection in I/O interface mode
UART mode
Table 14.8 Clock selection in UART mode
SC0CR<IOC>
Mode
SCLK output
Input/ output
SCLK input
selection
TMP19A44(rev1.3) 14-37
(Fixed to rising edge)
Clock edge selection
Baud rate generator
SC0MOD0<SC1:0>
SC0CR<SCLKS>
Clock selection
Falling edge
Rising edge
Timer output
SCLK input
fsys/2
Baud rate generator output
Rising edge of SCLK input
Falling edge of SCLK input
divided by 2
TMP19A44
Clock selection
2010-04-01

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