tmp19a44fda TOSHIBA Semiconductor CORPORATION, tmp19a44fda Datasheet - Page 573

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tmp19a44fda

Manufacturer Part Number
tmp19a44fda
Description
32bit Tx System Risc
Manufacturer
TOSHIBA Semiconductor CORPORATION
Datasheet

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23. JTAG Interface
Note)
JTAG Interface
23.1 Boundary Scan Overview
The TMP19A44 is equipped with the boundary scan interface that conforms to the Joint Test Action Group
(JTAG) standard. This interface uses the industry-standard JTAG protocol (IEEE Standard 1149.1/D6). This
chapter describes this JTAG interface with a mention of boundary scan, interface pins, interface signals, and test
access ports (TAP).
IC (Integrated Circuit) density is ever increasing, SMDs (Surface Mount Devices) continue to decrease in size,
components are now mounted on both sides of printed circuit boards (PCBs), and there are considerable
technical developments related to embedding holes. Conventional internal circuit testing techniques are
dependent on the physical contact between internal circuitry and chips and, therefore, their limitations with
respect to efficiency and accuracy are manifest. With the ever-increasing IC complexity, tests conducted to
perform inspections on all chips integrated into an IC are becoming larger in scale, and it is becoming more
difficult to design an efficient, reliable IC testing program.
To overcome this difficulty in performing IC tests, the "boundary scan" circuit was developed. It is a group of
shift registers called "boundary scan cells" established between pins and internal circuitry (see Fig. 23-1). These
boundary scan cells are bypassed under normal conditions. When an IC goes into test mode, data is sent from
the boundary scan cells through the shift register bus in response to the instruction given by a test program, and
various diagnostic tests are executed. In IC tests, five signals TDI, TDO, TMS, TCK and TRST are used. These
signals are explained in the next section.
The optional instructions IDCODE, USERCODE, INTEST and RUNBIST are not implemented
in the TMP19A44.
Fig. 23-1 JTAG Boundary Scan Cells
TMP19A44(rev1.3) 23-1
Integrated circuit
Pins on IC package
Boundary scan cells
TMP19A44
2010-04-01

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