tmp19a44fda TOSHIBA Semiconductor CORPORATION, tmp19a44fda Datasheet - Page 60

• Manufacturer Part Number: tmp19a44fda
• Description: 32bit Tx System Risc
• Manufacturer: TOSHIBA Semiconductor CORPORATION

Exceptions/Interrupts
6.1.3.6
Exception is
generated
ERET
execution
(Note) The ERET instruction copies the values in SSCR<CSS> to SSCR<PSS> regardless of
・When ERL=1 (Reset/ NMI is generated)
・EXL=1 (general exception/ interrupt other than reset/NMI is generated)
register when returning from the exception handler to the program previously executed. Please note that the same
exception/ interrupt may occur once again at that time.
(1) Returning with ERET instruction
executing the ERET instruction, the normal operation restarts from the address stored in the Error EPC／EPC of the
CP0 register, and the CP register automatically goes back to the pre-exception/interrupt state. If you set the
rewritable ErrorEPC／EPC with the return address in advance, the normal operation restarts from the desired
address by executing the ERET instruction.
below.
You can refer to the exception/ interrupt generation program counter stored in the ErrorEPC/ EPC of the CP0
To return from an exception handler of general exception/ interrupt, you can use the ERET instruction. By
The ERET instruction operates differently according to the setting of Status<ERL> and <EXL> bits as shown
（If SSD bit is “0” and a shadow register is available.）
When an exception is generated, “CSS” is copied to “PSS”, however, CSS remains
intact. That is, “CSS” values remain intact during and after handling exception.
Returning from Exceptions/ interrupts
the exception/interrupt to be executed.
0
0
Status<ERL>
SSCR<CSS>
Branch off to
Status<EXL>
SSCR<CSS>
Branch off to
SSCR
Exception is generated
2
2
SSD
0
TMP19A44(rev1.3) 6-10
←
←
←
←
←
←
“0”
“PSS”
Address stored in ErrorEPC
“0”
“PSS”
Address store in EPC
PSS
X
2
2
0
0
CSS
2
Interrupt is generated
2
2
TMP19A44
5
2
2010-04-01
Interrupt
is generated
( level 5)
ERET
execution