tmp19a44fda TOSHIBA Semiconductor CORPORATION, tmp19a44fda Datasheet - Page 252

• Manufacturer Part Number: tmp19a44fda
• Description: 32bit Tx System Risc
• Manufacturer: TOSHIBA Semiconductor CORPORATION

External Bus Interface
8.5 Bus Arbitration
The TMP19A44 can be connected to an external bus master. The arbitration of bus control authority with the
external bus master is executed by using the two signals, BUSRQ and BUSAK . The external bus master can
acquire control authority for TMP19A44 external buses only, and cannot acquire control authority for internal
buses.
(1) Accessible range of external bus master
(2) Acquisition of bus control authority
The external bus master can acquire control authority for TMP19A44 external buses only, and cannot
acquire control authority for internal buses (G-BUS). Therefore, the external bus master cannot access the
internal memories or the internal I/O. The arbitration of bus control authority for external buses is executed
by the external bus interface circuit (EBIF), and this is independent of the CPU and the internal DMAC.
Even when the external bus master holds the external bus control authority, the CPU and the internal
DMAC can access the internal ROM, RAM and registers. On the other hand, if the CPU or the internal
DMAC tries to access an external memory when the external bus master holds the external bus control
authority, the CPU or the internal DMAC has to wait until the external bus master releases the bus. For this
reason, if the BUSRQ remains active, the TMP19A44 can lock.
The external bus master requests the TMP19A44 for bus control authority by asserting the BUSRQ signal.
The TMP19A44 samples the BUSRQ signal at the break of external bus cycles on the internal buses (G-
BUS) and determines whether or not to give the bus control authority to the external bus master. When it
gives the bus control authority to the external bus master, it asserts the BUSAK signal. At the same time,
it makes address buses, data buses and bus control signals ( RD and WR ) in a state of high impedance.
(The internal pull-up is enabled for the
Depending on the relationship between the size of data to be loaded or stored and the external memory bus
width, two or more bus cycles can occur in response to a single data transfer (bus sizing). In this case, the
end of the last bus cycle is the break of external bus cycles.
If access to external areas occurs consecutively on the TMP19A44, a dummy cycle can be inserted. Again,
requests for buses are accepted at the break of external bus cycles on the internal buses (G-BUS). During a
dummy cycle, the next external bus cycle is already started on the internal buses. Therefore, even if the
completed.
Keep asserting the BUSRQ signal until the bus control authority is released.
Fig. 8.19 shows the timing of acquiring bus control authority by the external bus master.
BUSRQ signal is asserted during a dummy cycle, the bus is not released until the next external bus cycle is
TMP19A44 (rev1.3) 8-24
R/
W
, HWR and CSx .)
TMP19A44
2010-04-01