tmp19a44fda TOSHIBA Semiconductor CORPORATION, tmp19a44fda Datasheet - Page 230

• Manufacturer Part Number: tmp19a44fda
• Description: 32bit Tx System Risc
• Manufacturer: TOSHIBA Semiconductor CORPORATION

External Bus Interface
8.1 Address and Data Pins
(1) Address and data pin settings
Each port is put into input mode after a reset. To access an external device, set the address and data bus
functions by using the port control register (PnCR) and the port function register (PnFCm), and set the input
enable register (PnIE).
The TMP19A44 can be set to either separate bus or multiplexed bus mode. Setting the BUSMD pin (port
P45) to the "L" level (DVSS) at a reset activates the separate bus mode, and setting the pin to the "H" level
(DVCC3) activates the multiplexed bus mode. Port pins 0, 1, 2, 5 and 6, which are to be connected to
external devices (memory), are used as address buses, data buses and address/data buses. Table 8.1 shows
these.
Port 0 (P00 to P07)
Port 1 (P10 to P17)
Port 2 (P20 to P27)
Port 3 (P37)
Port 5 (P50 to P57)
Port 6 (P60 to P67)
Table 8.1 Bus Mode, Address and Data Pins
General-purpose port
TMP19A44 (rev1.3) 8-2
BUSMD (P45) ="L"
Separate
A16-A23
D8-D15
A8-A15
D0-D7
A0-A7
General-purpose port
General-purpose port
BUSMD (P45) ="H"
AD8-AD15/A8-A15
A0-A7/A16-A23
Multiplex
AD0-AD7
ALE
TMP19A44
2010-04-01