tmp19a44fda TOSHIBA Semiconductor CORPORATION, tmp19a44fda Datasheet - Page 293

• Manufacturer Part Number: tmp19a44fda
• Description: 32bit Tx System Risc
• Manufacturer: TOSHIBA Semiconductor CORPORATION

Internal system clock
DREQn
DACKn
ALE
A [23:16]
AD [15:0]
RD
WR
HWR
CSn
R/W
Internal system clock
DREQ
DACKn
ALE
A [23:16]
AD [15:0]
RD
WR
HWR
CSn
R/W
DMA Controller (DMAC)
10.5.2
•
•
DREQn-Initiated Transfer Mode
(7+α) clock
(7+α) clock
Fig. 10.19 Level Mode (from Internal RAM to External Memory)
Fig. 10.20 Level Mode (from External Memory to Internal RAM)
Data transfer from internal RAM to external memory (multiplexed bus, 5-wait insertion, level
mode)
Fig. 10.19 shows two timing cycles in which 16-bit data is transferred twice from internal
RAM to external memory (16-bit width).
Data transfer from external memory to internal RAM (multiplexed bus, 5-wait insertion, level
mode)
Fig. 10.20 shows two timing cycles in which 16-bit data is transferred twice from external
memory (16-bit width) to internal RAM.
Add
Add
TMP19A44 (rev1.3) 10-30
5 waits
5 waits
Add
Add
Data
Data
Add
Add
Data
TMP19A44
Data
2010-04-01