tmp19a44fda TOSHIBA Semiconductor CORPORATION, tmp19a44fda Datasheet - Page 397

• Manufacturer Part Number: tmp19a44fda
• Description: 32bit Tx System Risc
• Manufacturer: TOSHIBA Semiconductor CORPORATION

High-speed Serial Clock Generation Circuit
Receive Counter
Receive Control Unit
Receive Buffer
Serial Channel (HSIO)
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This circuit generates basic transmit and receive clocks.
The receive counter is a 4-bit binary counter used in the asynchronous (UART) mode and is up-counted
by HSIOCLK. Sixteen HSIOCLK clock pulses are used in receiving a single data bit while the data
symbol is sampled at the seventh, eighth, and ninth pulses. From these three samples, majority logic is
applied to decide the received data.
The receive buffer is of a dual structure to prevent overrun errors. The first receive buffer (a shift
register) stores the received data bit-by-bit. When a complete set of bits have been stored, they are
moved to the second receive buffer (HSC0BUF). At the same time, the receive buffer full flag
(HC0MOD2 "RBFLL") is set to "1" to indicate that valid data is stored in the second receive buffer.
However, if the receive FIFO is set enabled, the receive data is moved to the receive FIFO and this flag
is immediately cleared.
If the receive FIFO has been disabled (HSCOFCNF <CNFG> = 0 and <FDPX1:0> = 01/11), the
HINTRX0 interrupt is generated at the same time. If the receive FIFO has been enabled (HSCNFCNF
<CNFG> = 1 and SCOMOD1<FDPX1:0> = 01/11), an interrupt will be generated according to the
HSC0RFC <RIL1:0> setting.
I/O interface mode:
Asynchronous (UART) mode:
I/O interface mode:
Asynchronous (UART) mode:
In the HSCLK output mode with the HC0CR <IOC> serial control register set to "0," the output of
the previously mentioned baud rate generator is divided by 2 to generate the basic clock.
In the HSCLK input mode with HC0CR <IOC> set to "1," rising and falling edges are detected
according to the HC0CR <HSCLKS> setting to generate the basic clock.
According to the settings of the serial control mode register HSC0MOD0 <SC1:0>, either the
clock from the baud rate register, the system clock (f
timer, or the external clock (HSCLKO pin) is selected to generate the basic clock, HSIOCLK.
In the HSCLK output mode with HC0CR <IOC> set to "0," the HRXD0 pin is sampled on the
rising edge of the shift clock output to the HSCLK0 pin.
In the HSCLK input mode with HC0CR <IOC> set to "1," the serial receive data HRXD0 pin is
sampled on the rising or falling edge of HSCLK input depending on the HC0CR <HSCLKS>
setting.
The receive control unit has a start bit detection circuit, which is used to initiate receive operation
when a normal start bit is detected.
TMP19A44(rev1.3) 15-7
SYS
), the internal output signal of the TMRB3
TMP19A44
2010-04-01