tmp19a44fda TOSHIBA Semiconductor CORPORATION, tmp19a44fda Datasheet - Page 581

• Manufacturer Part Number: tmp19a44fda
• Description: 32bit Tx System Risc
• Manufacturer: TOSHIBA Semiconductor CORPORATION

JTAG Interface
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Shift-DR
If the TAP controller is in the Shift-DR state, data is serially shifted out by the data register
connected between TDI and TDO.
If the TAP controller is in the Shift-DR state, the Shift-DR state is maintained while TMS is "0."
If "1" is input into TMS, the TAP controller goes into the Exit 1-DR state.
Exit 1-DR
The Exit 1-DR state of the TAP controller is a transient state.
If "0" is input into TMS when the TAP controller is in the Exit 1-DR state, the TAP controller
goes into the Pause-DR state. If "1" is input into TMS, it goes into the Update-DR state.
Pause-DR
In the Pause-DR state, the shift operation performed by the data register selected by the
instruction register is temporarily suspended. The instruction register and the data register
maintain their existing state.
The TAP controller remains in the Pause-DR state while TMS is "0." If "1" is input into TMS, it
goes into the Exit 2-DR state.
Exit 2-DR
The Exit 2-DR state of the TAP controller is a transient state.
If "0" is input into TMS when the TAP controller is in the Exit 2-DR state, the TAP controller
returns to the Shift-DR state. If "1" is input into TMS, it goes into the Update-DR state.
Update-DR
In the Update-DR state, data is output in a parallel fashion from the data register having a parallel
output synchronously to the rising edge of TCK. The data register with a parallel output latch
does not output data during the shift operation; it outputs data only in the Update-DR state.
If "0" is input into TMS when the TAP controller is in the Update-DR state, the TAP controller
goes into the Run-Test/Idle state. If "1" is input into TMS, it goes into the Select-DR-Scan state.
Capture-IR
In the Capture-IR state, data is loaded into the instruction register in a parallel fashion. Data
loaded is 0001. The Capture-IR state is used to test the instruction register. A malfunction of the
instruction register can be detected by shifting out the data loaded.
If "0" is input into TMS when the TAP controller is in the Capture-IR state, the TAP controller
goes into the Shift-IR state. If "1" is input into TMS, it goes into the Exit 1-IR state.
Shift-IR
In the Shift-IR state, the instruction register is connected between TDI and TDO, and data loaded
synchronously to the rising edge of TCK is serially shifted out.
The TAP controller remains in the Shift-IR state while TMS is "0." If "1" is input into TMS, the
TAP controller goes into the Exit 1-IR state.
Exit 1-IR
The Exit 1-IR state of the TAP controller is a transient state.
If "0" is input into TMS when the TAP controller is in the Exit 1-IR state, the TAP controller goes
into the Pause-IR state. If "1" is input into TMS, it goes into the Update-IR state.
TMP19A44(rev1.3) 23-9
TMP19A44
2010-04-01