tmp19a44fda TOSHIBA Semiconductor CORPORATION, tmp19a44fda Datasheet - Page 443

• Manufacturer Part Number: tmp19a44fda
• Description: 32bit Tx System Risc
• Manufacturer: TOSHIBA Semiconductor CORPORATION

Serial Bus Interface (SBI)
SCL
SDA
<PIN>
INTS interrupt request
SCL pin
Write to SBI0DBR
SDA pin
<PIN>
INTS0 interrupt request
INTS0 interrupt
Receiver mode (<TRX> = "0")
If the next data to be transmitted has eight bits, the transmit data is written into SBIDBR. If the
data has different length, <BC2:0> and <ACK> are programmed and the received data is read from
SBIDBR to release the SCL line. (The data read immediately after transmission of a slave address
is undefined.) On reading the data, <PIN> is set to "1," and the serial clock is output to the SCL
pin to transfer the next data word. In the last bit, when the acknowledgment signal becomes the
"L" level, "0" is output to the SDA pin.
After that, the INTS0 interrupt request is generated, and <PIN> is cleared to "0," pulling the SCL
pin to the "L" level. Each time the received data is read from SBIDBR, one-word transfer clock
and an acknowledgement signal are output.
Fig. 16.10 <BC2:0> = "000" and <ACK> = "1" (Transmitter Mode)
if MST = 0
Then go to the slave-mode processing
if TRX = 0
Then go to the receiver-mode processing
if LRB = 0
Then go to processing for generating the stop condition
SBICR1
SBIDBR
End of interrupt processing
(Note) X: Don't care
Fig. 16.11<BC2:0> = "000" and <ACK> = "1" (Receiver Mode)
D7
D7
Read the received data
1
1
← X X X X 0 X X X
← X X X X X X X X
D6
D6
2
2
TMP19A44 (rev1.3) 16-19
D5
D5
3
3
D4
D4
4
4
Specifies the number of bits to be transmitted and specify whether
ACK is required.
Writes the transmit data.
D3
D3
5
5
D2
D2
6
6
D1
D1
7
7
D0
D0
TMP19A44
8
8
Master to slave
Slave to master
ACK
Master to slave
Slave to master
ACK
9
9
2010-04-01
Acknowledgment
signal from receiver
Acknowledgment
signal to transmitter
Next D7