tmp19a44fda TOSHIBA Semiconductor CORPORATION, tmp19a44fda Datasheet - Page 291

• Manufacturer Part Number: tmp19a44fda
• Description: 32bit Tx System Risc
• Manufacturer: TOSHIBA Semiconductor CORPORATION

DMA Controller (DMAC)
10.5 Timing Diagrams
DMAC operations are synchronous to the rising edges of the internal system clock.
10.5.1
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Dual Address Mode
Continuous transfer
Fig. 10.16 shows an example of the timing with which 16-bit data is transferred from one
external memory (16-bit width) to another (16-bit width). Data is actually transferred
successively until BCRn becomes "0."
Single transfer (1)
Fig. 10.17 shows an example of the timing with which data is transferred from one external
memory to another if the unit of data to be transferred is set to 16 bits and if the device port
size is set to 16 bits.
A [23 : 0]
D [15 : 0]
CS0
CS1
RD
WR
A [23 : 0]
D [15 : 0]
CS0
CS1
RD
WR / HWR
Fig. 10.17 Dual Address Mode (single transfer)
Fig. 10.16 Dual Address Mode (continuous)
tsys
TMP19A44 (rev1.3) 10-28
tsys
Read
Data
Read
Data
Write
Write
Data
Data
TMP19A44
Write
Data
2010-04-01