tmp19a44fda TOSHIBA Semiconductor CORPORATION, tmp19a44fda Datasheet - Page 586

• Manufacturer Part Number: tmp19a44fda
• Description: 32bit Tx System Risc
• Manufacturer: TOSHIBA Semiconductor CORPORATION

24. Flash Memory Operation
Flash Memory Operation
24.1 Flash Memory
This section describes the hardware configuration and operation of the flash memory.
24.1.1
1) Memory capacity
・ The TMP19A44F10XBG device contains 8M bits (1024 kB) of flash memory capacity. The
・ The TMP19A44FEXBG device contains 6M bits (768 kB) of flash memory capacity. The memory
・ The TMP19A44FDAXBG device contains 4M bits (512 kB) of flash memory capacity. The
・ Flash memory access: Interleave access is used in this device.
2) Write/erase time
3) Programming method
Rewriting method
The flash memory included in this device is generally compliant with the applicable JEDEC standards
except for some specific functions. Therefore, if the user is currently using an external flash memory
device, it is easy to implement the functions into this device. Furthermore, the user is not required to
build his/her own programs to realize complicated write and erase functions because such functions are
automatically performed using the circuits already built-in the flash memory chip.
This device is also implemented with a read-protect function to inhibit reading flash memory data from
any external writer device. On the other hand, rewrite protection is available only through command-
based software programming; any hardware setting method to apply +12VDC is not supported. The
above described protection function is enabled for each area respectively. When the user removes
protection, the internal data is automatically erased before the protection is actually removed.
Write time: 0.5 sec/128 Kbyte (Typ.)
Erase: 100 msec/1 block (Typ.)
The onboard programming mode is available for the user to program (rewrite) the device while it is
mounted on the user's board.
memory area consists of 10 independent memory blocks (128 kB × 7, 64 kB × 1 and 32 kB × 2) to
enable independent write access to each block. When the CPU is to access the internal flash
memory, 32-bit data bus width is used.
area consists of 8 independent memory blocks (128 kB × 5, 64 kB × 1 and 32 kB × 2).
memory area consists of 6 independent memory blocks (128 kB × 3, 64 kB × 1 and 32 kB × 2).
(Note)
4-1) User boot mode
4-2) Single boot mode
Features
The user's original rewriting method can be supported.
The rewriting method to use serial data transfer (Toshiba's unique method) can be supported.
The above values are theoretical values not including data transfer time.
The write time per chip depends on the write method to be used by the user.
TMP19A44F10XBG: 4sec (Typ)/ TMP19A44FDAXBG: 2 sec (Typ)
TMP19A44F10XBG: 1sec (Typ)/ TMP19A44FDAXBG: 0.6 sec (Typ)
TMP19A44 (rev1.3)24-1
TMP19A44
2010-04-01