tmp19a44fda TOSHIBA Semiconductor CORPORATION, tmp19a44fda Datasheet - Page 398

• Manufacturer Part Number: tmp19a44fda
• Description: 32bit Tx System Risc
• Manufacturer: TOSHIBA Semiconductor CORPORATION

Serial Channel (HSIO)
The CPU will read the data from either the second receive buffer (HSC0BUF) or from the receive FIFO
(the address is the same as that of the receive buffer). If the receive FIFO has not been enabled, the
receive buffer full flag <RBFLL> is cleared to "0" by the read operation. The next data received can be
stored in the first receive buffer even if the CPU has not read the previous data from the second receive
buffer (HSC0BUF) or the receive FIFO.
If HSCLK is set to generate clock output in the I/O interface mode, the double buffer control bit
HC0MOD2 <WBUF> can be programmed to enable or disable the operation of the second receive
buffer (HSCOBUF).
By disabling the second receive buffer (i.e., the double buffer function) and also disabling the receive
FIFO (HSCOFCNF <CNFG> = 0 or 1 and <FDPX1:0> = 10), handshaking with the other side of
communication can be enabled and the HSCLK output stops each time one frame of data is transferred.
In this setting, the CPU reads data from the first receive buffer. By the read operation of CPU, the
HSCLK output resumes.
If the second receive buffer (i.e., double buffering) is enabled but the receive FIFO is not enabled, the
HSCLK output is stopped when the first receive data is moved from the first receive buffer to the
second receive buffer and the next data is stored in the first buffer filling both buffers with valid data.
When the second receive buffer is read, the data of the first receive buffer is moved to the second
receive buffer and the HSCLK output is resumed upon generation of the receive interrupt HINTRX.
Therefore, no buffer overrun error will be caused in the I/O interface HSCLK output mode regardless of
the setting of the double buffer control bit HC0MOD2 <WBUF>.
If the second receive buffer (double buffering) is enabled and the receive FIFO is also enabled
(HSCNFCNF <CNFG> = 1 and <FDPX1:0> = 01/11), the HSCLK output will be stopped when the
receive FIFO is full (according to the setting of HSCOFNCF <RFST>) and both the first and second
receive buffers contain valid data. Also in this case, if HSCOFCNF <RXTXCNT> has been set to "1,"
the receive control bit RXE will be automatically cleared upon suspension of the HSCLK output. If it is
set to "0," automatic clearing will not be performed.
(Note)
In other operating modes, the operation of the second receive buffer is always valid, thus improving the
performance of continuous data transfer. If the receive FIFO is not enabled, an overrun error occurs
when the data in the second receive buffer (HSC0BUF) has not been read before the first receive buffer
is full with the next receive data. If an overrun error occurs, data in the first receive buffer will be lost
while data in the second receive buffer and the contents of HC0CR <RB8> remain intact. If the receive
FIFO is enabled, the FIFO must be read before the FIFO is full and the second receive buffer is written
by the next data through the first buffer. Otherwise, an overrun error will be generated and the receive
FIFO overrun error flag will be set. Even in this case, the data already in the receive FIFO remains
intact.
The parity bit to be added in the 8-bit UART mode as well as the most significant bit in the 9-bit UART
mode will be stored in HC0CR <RB8>.
In the 9-bit UART mode, the slave controller can be operated in the wake-up mode by setting the wake-
up function HSC0MOD0 <WU> to "1." In this case, the interrupt HINTRX0 will be generated only
when HC0CR <RB8> is set to "1."
In this mode, the HC0CR <OERR> flag is insignificant and the operation is
undefined.
another mode, the HC0CR register must be read to initialize this flag.
Therefore, before switching from the HSCLK output mode to
TMP19A44(rev1.3) 15-8
TMP19A44
2010-04-01