HD6417320 RENESAS [Renesas Technology Corp], HD6417320 Datasheet - Page 1072

• Manufacturer Part Number: HD6417320
• Description: Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

Section 30
In addition, the only D7 to D0 bits are inverted by the SINV bit. The O/E bit in SCSMR is set to
odd parity mode to invert the parity bit. In transmission and reception, the setting condition is
similar.
Rev. 3.00 Jan. 18, 2008 Page 1010 of 1458
REJ09B0033-0300
For the inverse-convention type, the logical level 1 is assigned to the A state, and the logical
level 0 to the Z state, and transmission and reception are performed in MSB-first. The data of
the start character shown in figure 30.3 is then H'3F. Even parity is used according to the smart
card specification, and so the parity bit is 0 corresponding to the Z state.
SIM Card Module (SIM)
(Z)
Figure 30.3
(Z)
(b) Inverse convention (SDIR=SINV=O/E=1)
(a) Direct convention (SDIR=SINV=O/E=0)
Ds
Ds
A
A
D7
D0 D1
Z
Z
D6
Z
Z
Examples of Start Character Waveforms
D5
D2
A
A
D4
D3
Z
A
D3
D4
Z
A
D2
D5
Z
A
D1
D6
A
A
D0
D7
A
A
Dp
Dp
Z
Z
(Z)
(Z)
state
state